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Production method of complementary metal-oxide-semiconductor transistor

A technology of oxide semiconductors and semiconductors, applied in semiconductor/solid-state device manufacturing, transistors, semiconductor devices, etc., can solve problems that affect the normal operation of complementary metal oxide semiconductor transistors, permanent loss of function, etc., and achieve improved lock-up prevention effect of ability

Active Publication Date: 2008-08-20
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Once the latch-up phenomenon occurs, the complementary metal oxide semiconductor transistor will temporarily or even permanently lose its function, which will affect the normal operation of the complementary metal oxide semiconductor transistor. Therefore, in the design and production process of the complementary metal oxide semiconductor transistor , how to avoid the occurrence of locked-in phenomenon has become an important topic in research and development

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  • Production method of complementary metal-oxide-semiconductor transistor
  • Production method of complementary metal-oxide-semiconductor transistor
  • Production method of complementary metal-oxide-semiconductor transistor

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Embodiment Construction

[0053] Please refer to Figure 4 , Figure 4 A flow chart of a method for fabricating a complementary metal-oxide-semiconductor transistor according to the first preferred embodiment of the present invention. Such as Figure 4 As shown, the main process steps of manufacturing CMOS transistors in this embodiment include:

[0054] Step 60: providing a semiconductor substrate;

[0055] Step 61: forming a doped well;

[0056] Step 62: forming an isolation structure;

[0057] Step 63: making a gate structure;

[0058] Step 64: making a lightly doped drain, a pocket-type doped region, and a deep-pocket doped region;

[0059] Step 65: making partition walls; and

[0060] Step 66: Make Source / Drain.

[0061] Please continue to refer Figure 5 to Figure 11 , Figure 5 to Figure 11 A schematic diagram of a method for fabricating a CMOS transistor according to the first embodiment of the present invention. In this embodiment, the first conductivity type is P-type, and the seco...

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Abstract

The invention provides a complementary metal oxide semiconductor transistor and the manufacturing method thereof. By arranging deep pocket doping region on a semiconductor substrate, locking phenomenon is avoided. In addition, since the manufacture of the deep pocket doping region is integrated into lightly doped drain process or source / drain doping region process, additional mask cost is not needed, so that locking prevention ability is effectively improved.

Description

technical field [0001] The present invention relates to a complementary metal oxide semiconductor transistor and a manufacturing method thereof, in particular to a complementary metal oxide semiconductor transistor with excellent latch-up robustness and a manufacturing method thereof. Background technique [0002] A Complementary Metal Oxide Semiconductor (CMOS) transistor is a semiconductor basic element composed of an N-type Metal Oxide Semiconductor (NMOS) transistor and a P-type Metal Oxide Semiconductor (PMOS) transistor. [0003] Please refer to figure 1 , figure 1 It is a schematic structural diagram of an existing complementary metal-oxide-semiconductor transistor. Such as figure 1 As shown, the existing complementary metal oxide semiconductor transistor includes a P-type semiconductor substrate 10, and the semiconductor substrate 10 in the bottom view direction can distinguish the P-type metal oxide semiconductor element region 20 and the N-type metal oxide semic...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8238H01L21/336H01L27/092H01L29/78
Inventor 陈铭逸赵芳玫
Owner UNITED MICROELECTRONICS CORP