Shift buffer

Abstract

Disclosed is a shift buffer, comprising shift buffering units which are sequentially connected in series. Each shift buffering unit, composed of a first and a second switch gears and a first and a second driving devices, generates output signals under the control of a first and a second time-pulse signals which are opposite to each other. The first switchgear provides output signals through an output node. The first driving device drives the first switchgear to activate the output signals according to the first input signal; the second driving device is coupled with a first voltage signal and conveys the first voltage signal according to the first time pulse signal to drive the first switchgear to not activate the output signals. When the first switchgear does not activate the output signals, the second switchgear provides a second voltage signal to the output node according to the second time-pulse signal. The level of the first voltage signal is lower than the level of the second voltage signal. The shift buffer can avoid the occasion that the shift buffering units are out of normal work when the critical voltage of the transistor offset.

Description

technical field [0001] The present invention relates to a shift register, in particular to a shift register unit, the output signal of which is not affected by the shift of the critical voltage of the internal transistor. Background technique [0002] In the current LCD panel design, the scan signal and the data signal are generated by the gate driver and the source driver. In order to reduce the cost, a shift register with the same circuit function as the gate driver is arranged on the glass substrate. However, since the shift register mostly adopts the technology of amorphous silicon thin film process, after the display panel is lit, the panel display is abnormal due to the influence of stress on the transistor. [0003] Fig. 1 shows a shift register unit of a known shift register. FIG. 2 is a signal timing diagram showing a known shift register unit. Referring to FIG. 1 and FIG. 2 , the shift register unit 1 is controlled by clock signals CK and XCK which are opposite ...

AI Technical Summary

Problems solved by technology

When the threshold voltage of the transistor of the shift register unit 1 deviates, the shift register unit 1 cannot operate normally, resulting in an incorrect output signal S N

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