Clock switch circuit

Abstract

The invention discloses a clock commutation circuit, which resolves technical problem of producing bur and metastable state. The clock commutation circuit of the invention is composed of two reset producing circuits, two OR gates, three NOT gates, two D-flip-flops and a clock output circuit, the reset producing circuits and the NOT gates constitutes a RS latch. Compared with the prior technology, when the first clock is switched to the second clock, the gating signal of the first clock is switched off when the first clock is at a low level, meanwhile the reset outputting signal of the second RS latch is released, the gating signal of the second clock is switched-on when the second clock is at a low level, thereby avoiding the bur during the clock switch. The reset producing circuit ensures that the asynchronous reset terminal of the D-flip-flop executes the synchronization operation to the reset signal through the RS latch circuit when the clock is at a low level, thereby avoiding the production of metastable state.

Description

technical field [0001] The invention relates to a clock circuit, in particular to a circuit for converting two clock signals. Background technique [0002] At present, many circuit applications need to switch the clock frequency. For example, different clock frequencies are required for receiving data and returning data during data communication, which requires switching between clocks of different frequencies. The clock switching circuit in the prior art has the following deficiencies: 1. A burr will be generated during clock switching, and the burr may cause subsequent flip-flops to act on the burr, which will lead to the occurrence of erroneous actions and eventually lead to functional errors; 2. The generation of metastable state. Some clock switching circuits use feedback to connect the output of a clock flip-flop to the input of another clock flip-flop. Due to the asynchronous relationship between clocks, it is likely to cause a metastable state. The generation, so th...

AI Technical Summary

Problems solved by technology

The clock switching circuit in the prior art has the following deficiencies: 1. A burr will be generated during clock switching, and the burr may cause subsequent flip-flops to act on the burr, which will lead to the occurrence of erroneous actions and eventually lead to functional errors; 2. The generation of metastable state. Some clock switching circuits use feedback to connect the output of a clock flip-flop to the input of another clock flip-flop. Due to the asynchronous relationship between clocks, it is likely to cause a metastable state. generation, thus making the circuit in an unpredictable state

The above problems will cause the application circuit to go wrong

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