58results about How to "Avoid metastability" patented technology

The invention discloses a clock commutation circuit, which resolves technical problem of producing bur and metastable state. The clock commutation circuit of the invention is composed of two reset producing circuits, two OR gates, three NOT gates, two D-flip-flops and a clock output circuit, the reset producing circuits and the NOT gates constitutes a RS latch. Compared with the prior technology, when the first clock is switched to the second clock, the gating signal of the first clock is switched off when the first clock is at a low level, meanwhile the reset outputting signal of the second RS latch is released, the gating signal of the second clock is switched-on when the second clock is at a low level, thereby avoiding the bur during the clock switch. The reset producing circuit ensures that the asynchronous reset terminal of the D-flip-flop executes the synchronization operation to the reset signal through the RS latch circuit when the clock is at a low level, thereby avoiding the production of metastable state.

The invention discloses a multi-channel parallel acquisition system with a storage function and a synchronous recognition function. In the N FPGA modules of the multi-channel parallel acquisition system, the first FPGA module generates valid trigger signals according to the trigger signal of a trigger channel and sends the valid trigger signals to the second FPGA module; and each FPGA module in the second FPGA module to the N-th FPGA module is configured with a delay module and a synchronous recognition module; the synchronous recognition modules are adopted to set the delay values of the delay modules according to the serial numbers of the corresponding FPGA modules in the initialization of the multi-channel parallel acquisition system; and the delay modules receive the valid trigger signals of the previous FPGA modules in the actual operation of the multi-channel parallel acquisition system, and delay the valid trigger signals according to the delay values, and send the delayed valid trigger signals to corresponding trigger modules, so that valid trigger signals can be generated. According to the multi-channel parallel acquisition system of the invention, the valid trigger signals in the FPGA modules in the multi-channel parallel acquisition system are accurately recognized and controlled, so that the correctness of the storage of data sequences of a back-end can be ensured.

The invention discloses an SEU (single event upset)/SET (single event transient)-resistant dynamic comparator, which comprises a pulse generating circuit based on a sensitive amplifier structure and an output latch circuit; the top of the whole comparator is provided with five input ports and four output ports outwards, the five input ports are respectively connected with clock signals, input signals and reference voltage signals, and the output ports are connected with data output signals; the pulse generating circuit is connected with the clock signals, the input signals, the reference voltage signals and the output latch circuit; and the output latch circuit is connected with the pulse generating circuit and the data output signals. The dynamic comparator has the advantages that the upset threshold LETth is greater than 500MeV/ (mg.cm2); the time delay is reduced while the high-speed low power consumption of the SEU/SET-resistant dynamic comparator same as that of a traditional dynamic comparator is achieved; the symmetrical arrangement, equal time delay and same drive capacity of complementary output terminals Q and QB are realized; by adopting the sensitive amplifier structure, the clock network is simple, reliable and small in load; and by adopting the minor clock swing technology, the power consumption is obviously reduced.

Method and system for controllably and sequentially powering up subsystems of an electronic system, device or integrated circuit. In one example, a first supply voltage is selectively applied to a first subsystem, and when the first supply voltage has reached a predetermined value, a second supply voltage is selectively applied to the second subsystem. The first and second supply voltages may also be boosted to provide fast startup timing. In this manner, the first subsystem is powered-up before the second supply voltage is applied to the second subsystem—this provides for controlled, sequential power up of the subsystems of the electronic system, device or integrated circuit.

The invention relates to the technical field of power supply management chips, in particular to a digital pulse width modulation circuit, which comprises a coarse delay module based on a counter, a clock management module based on a phase-locked loop, a two-stage synchronous trigger circuit module, a fine delay module based on a carry chain unit, a duty ratio decoding module and a gated clock unit. The invention has the beneficial effects that two-stage synchronous triggers are used on two main paths of high-level output triggering and asynchronous fine phase shift clock signals. Delay of different paths is balanced. Meanwhile, the rising edge of the input clock is prevented from being very close to the rising edge of the fine phase shift clock trigger signal. The clock management module is used for obtaining four paths of signals with the phase difference of 90 degrees, and after the four paths of phase shift clock signals pass through the gating clock unit and the fine delay module,the response speed of digital switch converter voltage regulation and control is increased.

The present invention provides method and apparatus for synchronizing data between different clock domains in a memory controller. In one embodiment, a memory controller is provided that includes a command decoder and synchronizing logic. The command decoder is operable to receive a command in accordance with a first clock domain. The synchronizing logic synchronizes the command to a second clock domain that is different from the first clock domain, and includes a first synchronization flop and a second synchronization flop operable to prevent metastability associated with synchronizing the command to the second clock domain.

The invention discloses a high-stability APUF circuit based on feedback time delay differential adjustment. The circuit comprises a PUF delay chain module, a positive hopping signal loading module, afeedback control module, a timer module and an arbiter. The positive hopping signal output by the PUF delay chain module is fed back to be applied to the PUF delay chain module again, the difference of the time sequence from the positive hopping signals to the arbiter in upper and lower paths is enlarged so as to overcome the semi-stable state of the arbiter, the arbiter stably outputs 0 or 1, andtherefore the APUF stability is improved. The high-stability APUF circuit has the advantages of being high in stability, easy to obtain, low in resource consumption and the like.

The invention discloses a control circuit for converting an asynchronous interface into a synchronous interface and relates to the technical field of integrated circuits. According to the control circuit, through combination of a reading clock detection unit, a writing clock detection unit, a first monostable unit, a second monostable unit and a delay control unit, conversion from the asynchronousinterface into the synchronous interface is realized, synchronous transmission of data is completed, communication between the external asynchronous interface and a local synchronous circuit is realized, conversion is completed in one cycle, signal conversion efficiency is improved, and a metastable state is avoided.

The invention provides a hard-disc Active-lamp constant-frequency-flickering control system and method. The method includes the steps that reading-and-sporting action information of a hard disc is obtained through a hard-disc edge detection module, and the ACTIVVITY edge information of the hard disc is sent to a flickering frequency control module; the flickering frequency control module receives the ACTIVVITY edges of the hard disc, and all the ACTIVVITY edges of the hard disc are measured through a built-in counter; when the hard disc is located on the ACTIVVITY edges, control signals ACT-OUT are located at the low level, and the hard disc is located at a non-ACTIVITY edge, the control signals ACT-OUT are in the original state; the ACT-OUT level state is detected in real time through an output control module, and when ACT-OUT is located at the low level, LED lamps are controlled to be lighted on; when ACT-OUT is located at the high level, the LED lamps are controlled to be lighted off. Misjudging of users when the flickering frequencies of the LED lamps of all the hard discs are inconsistent is prevented.

The invention belongs to the technical field of integrated circuit designing, particularly a comparator without a metastable state. The comparator consists of a reference voltage source Vref, a dithering voltage source Vd(t) and a hysteresis comparator T1. Input voltage Vin is connected with the input end a of the hysteresis comparator T1. The reference voltage source Vref is connected with the input end b of the hysteresis comparator T1 after being connected in series with the dithering voltage source Vd(t) with the direct current level of 0. The output end c of the hysteresis comparator T1 is connected with output voltage Vout. Dithering is added to the reference voltage, thereby avoiding the metastable state of the output of the comparator.

The invention provides a clock switching circuit of a gigabit Ethernet transceiver. According to the circuit, smooth switching of different clock domains is achieved through a three-level synchronization and interlocking mechanism, the risk that burrs and metastable states are generated due to clock switching across the clock domains is avoided, the correctness of circuit functions is guaranteed,a correct output clock can be provided during resetting, and the logic function of a chip during resetting is guaranteed.

An integrated-circuit device comprises a source register in a reset domain, a destination circuit outside the reset domain, and a reset checking circuit. The checking circuit comprises a buffer outside the reset domain for receiving data values output by the source register, a reset detector, and reset checking logic. The checking logic detects a new data value output by the source register, checks whether a reset of the reset domain has been detected, and contingently outputs a control signal for controlling whether the destination circuit receives the new data value from the buffer. The reset detector signals whether a reset has been detected by using a feedback path to hold a predetermined value in a resettable latch until the latch receives a reset signal, and to hold a different value in the latch after receiving a reset signal.

The invention provides an asynchronous pulse synchronizer. The asynchronous pulse synchronizer comprises an input logic unit, a meta-stable elimination unit and an output logic unit; the input logic unit is used for flattening pulse signals of an input clock domain into level signals, wherein an exclusive or gate and a D trigger are included; the meta-stable elimination unit comprises three D triggers; and the output logic unit is used for converting the level signals of an output clock domain into the pulse signals, wherein an exclusive or gate and a D trigger are included. The asynchronous pulse synchronizer provided by the invention can convert the pulse signals of a clock domain into the pulse signals of another asynchronous clock domain in digital circuit cross-clock-domain design; and furthermore, the meta-stable state of the signals in a synchronous process can be prevented.