Multi-channel parallel acquisition system with storage function and synchronous recognition function

Abstract

The invention discloses a multi-channel parallel acquisition system with a storage function and a synchronous recognition function. In the N FPGA modules of the multi-channel parallel acquisition system, the first FPGA module generates valid trigger signals according to the trigger signal of a trigger channel and sends the valid trigger signals to the second FPGA module; and each FPGA module in the second FPGA module to the N-th FPGA module is configured with a delay module and a synchronous recognition module; the synchronous recognition modules are adopted to set the delay values of the delay modules according to the serial numbers of the corresponding FPGA modules in the initialization of the multi-channel parallel acquisition system; and the delay modules receive the valid trigger signals of the previous FPGA modules in the actual operation of the multi-channel parallel acquisition system, and delay the valid trigger signals according to the delay values, and send the delayed valid trigger signals to corresponding trigger modules, so that valid trigger signals can be generated. According to the multi-channel parallel acquisition system of the invention, the valid trigger signals in the FPGA modules in the multi-channel parallel acquisition system are accurately recognized and controlled, so that the correctness of the storage of data sequences of a back-end can be ensured.

Description

technical field [0001] The invention belongs to the technical field of high-speed data acquisition, and more specifically relates to a multi-channel parallel acquisition system with a storage synchronization identification function. Background technique [0002] With the rapid development of science and technology, the frequency and bandwidth of digital signals also increase sharply, which puts forward higher requirements for the indicators of electronic measuring instruments. After using the time-alternating analog-to-digital conversion (TIADC) technology in parallel mode to successfully realize the high-frequency signal acquisition function of the high-speed acquisition system, how to stably store the generated high-speed data stream has become a problem for the stable operation of the acquisition system. one of the important research parts. [0003] The existing research on the synchronization problem of TIADC system mainly focuses on the reset synchronization problem be...

AI Technical Summary

Problems solved by technology

Before the read and write enable control of the data storage module, the effective trigger signal has to go through FPGA internal logic delay and circuit board delay, and these delay times are not easy to be accurately controlled, so the trigger signal is different from the internal operating clock of the system. source, it is possible that the trigger signal is just in the metastable interval of the running clock, which will lead to the uncertainty of the read and write control operations, and then cause data processing errors

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