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Extensible multi-port DDR3 controller based on FPGA

A controller and multi-port technology, which is applied in the field of communication, can solve problems such as the inability to meet the multi-port application requirements of simultaneously processing multiple high-speed complex data stream buffers, and achieve high use efficiency, memory space saving, and convenient read and write operations Effect

Active Publication Date: 2020-08-25
ウーハン ジョンケ ニウジン マグネティック レゾナンス テクノロジー カンパニー リミテッド
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Based on the technical problems existing in the background technology, the present invention proposes an expandable multi-port DDR3 controller based on FPGA, which has the characteristics of more convenient read and write operations and higher utilization efficiency of DDR3, and solves the problems that cannot be satisfied by the existing technology. Simultaneously handle the multi-port application requirements of multiple high-speed complex data stream buffers

Method used

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  • Extensible multi-port DDR3 controller based on FPGA
  • Extensible multi-port DDR3 controller based on FPGA
  • Extensible multi-port DDR3 controller based on FPGA

Examples

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Embodiment 1

[0036] A scalable multi-port DDR3 controller based on FPGA, including an arbitration module, a read-write space size management module, a DDR3 IP core control module and a FIFO interface control module, an arbitration module, a read-write space size management module, and a DDR3IP core control module and the FIFO interface control module are electrically connected in sequence;

[0037] The arbitration module is used to comprehensively arbitrate and manage the read and write requests of each port according to the remaining available address space for reading and writing provided by the read and write space size management module, the FIFO capacity threshold corresponding to each port, and the priority information of each port according to actual needs ;

[0038] The read and write space size management module is used to manage the read and write process of each port. According to the single read and write size configured globally and the total address space size of each port, t...

Embodiment 2

[0082] The difference technology compared with embodiment one is as follows:

[0083] Replace the read-write space size management module with the signal interface logic control module, which is used to configure the number of ports according to the port expansion requirements, and the DDR3 IP core control module and FIFO interface control module are also used to send and receive signal interface logic control module data. Configure the number of ports and the size of a single read and write. The number of ports determines the number of instantiated read and write FIFOs in the signal interface logic control module. FIFOs solve the problems of data caching and data transmission across clock domains.

[0084] The number of ports in this technical solution is configurable: the user can configure the number of data flow channels according to actual usage requirements, and the read-write interface adopts the standard FIFO interface form, which makes the read-write operation more co...

Embodiment 3

[0086] The difference technology compared with embodiment one is as follows:

[0087]On the basis of Embodiment 1, a signal interface logic control module is added, the signal interface logic control module is used to configure the number of ports according to the port expansion requirements, and the DDR3 IP core control module and FIFO interface control module are also used for sending and receiving signal interface logic control module data. Configure the number of ports and the size of a single read and write. The number of ports determines the number of instantiated read and write FIFOs in the signal interface logic control module. FIFOs solve the problems of data caching and data transmission across clock domains.

[0088] This technical solution provides a DDR3 controller interface whose number of ports can be arbitrarily expanded according to requirements, with standard FIFO read-write interface form, configurable port number, configurable single read-write size, and co...

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Abstract

The invention relates to the technical field of communication, and especially relates to an extensible multi-port DDR3 controller based on an FPGA. The controller comprises an arbitration module, a read-write space size management module, a DDR3 IP core control module and an FIFO interface control module, and the arbitration module, the read-write space size management module, the DDR3 IP core control module and the FIFO interface control module are electrically connected in sequence. The arbitration module is used for comprehensively arbitrating and managing the read-write request of each port according to the size of the read-write residual available address space provided by the read-write space size management module, the FIFO capacity threshold corresponding to each port and the priority information of each port arranged according to the actual demand. The controller has a standard FIFO read-write interface form, the number of ports is configurable, the size of single read-writeis configurable, the total size of the address space of each port is configurable, and the read-write priority arbitration of each port is provided in the controller.

Description

technical field [0001] The invention relates to the technical field of communication, in particular to an expandable multi-port DDR3 controller based on FPGA. Background technique [0002] With the rapid development of semiconductor memory technology, DDR3 memory particles have the advantages of large capacity, high read and write speed, and stable operation. Therefore, DDR3 memory has been widely used in computer, electronic communication and other fields. FPGA field programmable gate array has super large logic gate resources, can process multiple complex data streams at the same time, and can realize a variety of complex algorithms, so it is widely used in communication, image processing and other fields. [0003] The DDR3 hard-core resource interface of the latest kintex-7 series FPGA on the market realizes the physical layer connection of DDR3PHY, but its hard-core IP only provides users with a single read-write interface, including read-write address input app_addr, re...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/16G06F15/78
CPCG06F13/1605G06F13/1668G06F15/7807
Inventor 夏明敏李正刚朱天雄
Owner ウーハン ジョンケ ニウジン マグネティック レゾナンス テクノロジー カンパニー リミテッド
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