Synchronous hybrid delayed type DPWM module based on FPGA

Abstract

The invention discloses a synchronous hybrid delayed type DPWM structure obtained on the basis of an FPGA. A sub-module of the DPWM structure comprises a rising edge triggering circuit based on a counter, a synchronous clock generation module based on a phased-locked loop (PLL), a falling edge triggering circuit, a pulse width modulating wave output module based on a register, and a duty ratio synchronous encoding module. The linearity and stability of the time resolution ratio and duty ratio of a pulse width modulator can be improved, the ripple waves and stable time of a DC-DC converter arereduced and shortened, and the overshooting and ringing in the modulating process are restrained and weakened; meanwhile, due to the hybrid structure of the counter and a delay chain, the defects thata monotonous structure is limited in frequency and too large in occupied resource can be avoided, the working frequency range of the DPWM is expanded, and the resources occupied by the circuits are educed.

Description

technical field [0001] The invention relates to the field of power management chips, in particular to a DPWM module used in power management control circuits. Background technique [0002] The digital pulse width modulator (DPWM) has been developed for a long time. The traditional digital pulse width modulator is limited by the sampling delay and resolution. At the same time, the traditional digital pulse width modulator uses a single counter delay or A single delay chain delay is implemented. These single structures are limited by the operating frequency of the counter and the high circuit resource occupancy of the delay chain, and it is difficult to achieve high precision within limited design indicators. Therefore, optimizing the structure of DPWM, reducing the circuit resources used in the design, increasing the operating frequency, improving the linearity, resolution and stability of DPWM are major challenges for current digital pulse width modulators. Contents of the...

AI Technical Summary

Problems solved by technology

[0002] The digital pulse width modulator (DPWM) has been developed for a long time. The traditional digital pulse width modulator is limited by the sampling delay and resolution. At the same time, the traditional digital pulse width modulator uses a single counter delay or A single delay chain delay is implemented. These single structures are limited by the operating frequency of the counter and the high circuit resource occupancy rate of the delay chain, and it is difficult to achieve high precision within limited design indicators.

Images