Synchronous hybrid delayed type DPWM module based on FPGA
A delay chain and synchronous circuit technology, applied in the direction of pulse duration/width modulation, etc., can solve the problem of limited counter operating frequency, delay chain, high circuit resource occupancy, difficulty in achieving high precision, and limited digital pulse width modulator Problems such as sampling delay and resolution achieve the effect of high production cost, guaranteed accuracy and high linearity
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[0032] In this embodiment, the 14-bit DPWM structure is taken as an example (but not limited to 14 bits). An FPGA-based synchronous hybrid delay chain type DPWM module includes: a rising edge trigger circuit, a falling edge trigger circuit, and a duty cycle synchronous decoding circuit, register and phase-locked loop clock generation circuit;
[0033] The falling edge trigger circuit includes: two phase shift synchronous circuits, an addition and carry chain reset signal generation circuit;
[0034] The duty cycle synchronous decoding circuit acquires the n-bit duty cycle signal and performs segmentation processing, and sends the n-bit to the m-bit duty cycle signal D[n:m] of the n-bit duty cycle signal to the rising edge The trigger circuit decodes the m-1 to m-3 duty signal D[m-1:m-3] to obtain a four-digit digital signal D 2 [3:0] is sent to the falling edge trigger circuit, and the duty ratio signal D[m-4:0] from the m-4th bit to the 0th bit is decoded to obtain 2 m-4 bi...
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