Asynchronous pulse synchronizer

A pulse synchronous and asynchronous technology, applied in the direction of logic circuit connection/interface layout, logic circuit interface device, etc., can solve the problems of unpredictable and unpredictable unit output level, and achieve the effect of preventing metastable state

Pending Publication Date: 2019-04-19
天津国芯科技有限公司
View PDF7 Cites 1 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When a flip-flop goes metastable, there is no way to predict the output leve

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Asynchronous pulse synchronizer
  • Asynchronous pulse synchronizer
  • Asynchronous pulse synchronizer

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 2

[0028] Embodiment 2, if the timing problem is considered, the output of the output logic unit can be changed to register output, that is, according to the attached figure 2 A circuit is designed to resynchronize the output of the fifth D flip-flop (S104) by one stage before outputting, that is, a sixth D flip-flop is also included, and the input end of the sixth D flip-flop is connected to the output end of the second XOR gate.

[0029] The waveform diagram of the asynchronous pulse from high frequency to low frequency synchronous process in this embodiment is as follows image 3 As shown, the waveform diagram of the synchronous process of asynchronous pulse from low frequency to high frequency is as follows Figure 4 shown.

[0030] This embodiment supports an input clock clk_s with any frequency phase and an output clock clk_d with any frequency phase.

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention provides an asynchronous pulse synchronizer. The asynchronous pulse synchronizer comprises an input logic unit, a meta-stable elimination unit and an output logic unit; the input logic unit is used for flattening pulse signals of an input clock domain into level signals, wherein an exclusive or gate and a D trigger are included; the meta-stable elimination unit comprises three D triggers; and the output logic unit is used for converting the level signals of an output clock domain into the pulse signals, wherein an exclusive or gate and a D trigger are included. The asynchronous pulse synchronizer provided by the invention can convert the pulse signals of a clock domain into the pulse signals of another asynchronous clock domain in digital circuit cross-clock-domain design; and furthermore, the meta-stable state of the signals in a synchronous process can be prevented.

Description

technical field [0001] The invention belongs to the field of digital circuits, in particular to an asynchronous pulse synchronizer in a digital circuit. Background technique [0002] With the increase of the complexity of the current SOC design, the problem of multi-clock domain design is an inevitable problem in the current SOC design. If the logic is not clearly thought out during design, this problem can only be found in the post-simulation stage, which will increase the number of design iterations and prolong the design cycle. [0003] Metastability is the failure of a flip-flop to reach an identifiable state within a specified period of time. When a flip-flop goes metastable, there is no way to predict the cell's output level, nor when the output will settle to a certain correct level. During this stable period, the flip-flop outputs some intermediate level, or possibly oscillates, and this unwanted output level can cascade down the signal path to each flip-flop. [...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): H03K19/0175
CPCH03K19/017509
Inventor 王勇郑茳肖佐楠
Owner 天津国芯科技有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap