Method and device for optimizing chip layout of silicon slice

Abstract

The invention discloses a method for chip layout in an optimized silicon chip, which comprises the steps that: the layout parameters of the silicon chip is obtained, comprising the washing edge width, the plain edge height and the large plain edge length of the silicon chip; the exposure field wafer map of the silicon chip is generated according to the obtained layout parameters; the chip layout is carried out to the silicon chip according to the generated wafer map. The invention also discloses a device used for optimizing the chip layout in the silicon chip, the wafer map is determined according to the layout parameters; and fine adjustment is carried out to the wafer map by offset so as to cause the wafer map to be more close to the real silicon chip, and the effective area of the silicon chip can be fully utilized, thus causing the gross die of the effective chips of the layout on the silicon chip to be maximized.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method and a device for optimizing chip layout in a silicon chip. Background technique [0002] With the development of semiconductor technology, as well as the increasing requirements for the miniaturization of electronic devices and circuit integration density in the semiconductor industry, in the process of semiconductor wafer processing, it is usually necessary to integrate as many chips as possible on the silicon wafer, so as to make better use of the silicon wafer area. The so-called wafer refers to the silicon chip used in the production of semiconductor integrated circuits. Since the shape of the silicon chip is circular, it is also called a wafer. Silicon wafers are the most commonly used semiconductor materials. Current silicon wafers include various sizes such as 4 inches (inch), 5 inches, 6 inches, 8 inches and 12 inches, wherein 4 inches, 5 inches, 6 inches...

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Problems solved by technology

[0005] In view of this, the main purpose of the present invention is to provide a method and device for optimizing chip layout in silicon wafers, so as to solve the problem of unreasonable chip layout in silicon wafers in the prior art

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