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Method for accessing to a data transmission bus, corresponding device and system

A data bus and data access technology, applied in the fields of electronics and computing, can solve the problems of unguaranteed transmission bandwidth and delay, unsuitable for division, and unsuitable for low-level communication

Inactive Publication Date: 2008-12-24
THOMSON LICENSING SA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] This technique has the following inconvenience: the transmission bandwidth and delay for each host are not guaranteed
In addition, the bus is not suitable for low-level communication (such as physical layer type or PHY) or access to communication channels called media access control (MAC)
It is also not suitable for dividing between software and hardware resources

Method used

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  • Method for accessing to a data transmission bus, corresponding device and system
  • Method for accessing to a data transmission bus, corresponding device and system
  • Method for accessing to a data transmission bus, corresponding device and system

Examples

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Embodiment Construction

[0049] figure 1 A communication system 1 according to a particular embodiment of the invention is schematically shown.

[0050] System 1 includes:

[0051] - bus 10,

[0052] - an arbiter 13, which manages access to the bus 10;

[0053] - the primary master peripheral 100, which has the highest priority for accessing the bus 10;

[0054] - secondary host peripherals 110 to 112 connected to the bus 10; and

[0055] - From machine 120 to 123.

[0056] Hosts 110 to 112 are adapted to initiate data transfers on the bus in read and / or write modes. It has a lower priority for accessing the bus 100 than the primary master 100 . Advantageously, the number of hosts is not limited and can take any value (eg 3, 10, or 100). The greater the number of masters, the better the management of access authorization to the bus is required, and the lower the average time and transfer bandwidth allocated to each master. When the number of hosts is large, the present invention first makes a...

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Abstract

The invention relates to a bus (10) which is connectable to a primary master (22) and to secondary masters (32) and is used for transmitting data between peripherals. In order to ensure a minimum rate and / or maximum latency between the secondary masters when the primary master uses a small time fraction available on the bus, said primary master is provided with a high priority and comprises means for wirelessly accessing to a medium. The inventive method for accessing to the bus consists in authorising the primary master to access to the bus upon the request thereof and in selecting the access to the buss for the secondary master when the primary master peripheral does not request said access to the bus.

Description

technical field [0001] The present invention relates to the fields of electronics and computing, and more particularly, to a deterministic high-performance bus. Background technique [0002] According to the prior art, in the patent application US6,587,905 filed by International Business Machines Corporation with respect to Figure 9 A Processor Local Bus (PLB) is described comprising several slaves and masters. In addition, the access priority to the bus is defined for the master. In a PLB, the master with the lowest priority can only access the bus when other masters accessing the bus release the bus. [0003] This technique has the inconvenience that transfer bandwidth and delay for each host are not guaranteed. In addition, the bus is not suitable for low-level communication (such as physical layer type or PHY) or access to a communication channel called Media Access Control (MAC). It is also not suitable for dividing between software and hardware resources. Content...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/36
CPCG06F13/364G06F13/36G06F13/366
Inventor 雷诺·多尔卢多维克·珍妮帕特里克·洛佩斯
Owner THOMSON LICENSING SA
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