Method for fabricating semiconductor device with vertical channel

Abstract

A method for fabricating a semiconductor device with a vertical channel includes providing a substrate over which a hard mask pattern is formed, forming pillars over the substrate using the hard mask pattern thereby forming a resultant structure, forming an insulation layer over the resultant structure, planarizing the hard mask pattern and the insulation layer until the pillars are exposed, and forming a storage electrode over the exposed pillars.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 2007-0062782 filed on Jun. 26, 2007, the contents of which are incorporated herein by reference. technical field [0003] The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having a vertical channel. Background technique [0004] The channel length of a transistor decreases as the degree of integration of semiconductor devices increases. However, the reduced transistor channel length leads to short channel effects such as drain-induced barrier lowering (DIBL) phenomenon, hot carrier effect, and punch-through effect. Various methods have been proposed to eliminate the short channel effect, such as reducing the depth of the junction region and increasing the relative channel length by forming a recess in the channel region of the transistor. [00...

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Problems solved by technology

Thereafter, an electrical short may occur between the contact plug 308 and the word line 302 or around the gate electrode 304 and cause device failure

[0023] In addition, after removing the hard mask pattern 305, forming the contact plug 308 and the storage electrode in the remaining space complicates the method of manufacturing the semiconductor device.

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