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Semiconductor device with field plate and method

A semiconductor and device technology, applied in the field of semiconductor devices with recessed field plates and their fabrication

Active Publication Date: 2010-11-03
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This means that if this structure is to be integrated with a standard CMOS process, a considerable increase in complexity is required
[0007] A further difficulty is that some steps in this design may not be compatible at all with modern CMOS processes

Method used

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  • Semiconductor device with field plate and method
  • Semiconductor device with field plate and method
  • Semiconductor device with field plate and method

Examples

Experimental program
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Embodiment Construction

[0058] A method of fabricating an NMOS transistor according to an embodiment of the present invention will now be described.

[0059] First, if figure 1 with figure 2 As shown, a silicon-on-insulator (SOI) substrate 2 is provided in which a single crystal silicon device layer 10 is formed on an insulating layer 12 . In this embodiment, the insulating layer is a buried oxide layer, but in alternative embodiments, other silicon-on-insulator technologies, such as silicon-on-sapphire technology, may be used.

[0060] The silicon device layer 10 in an embodiment is 60nm thick.

[0061] Such as figure 1 (top view) and figure 2 As shown in (side view), the first process step is to form a U-shaped insulating region 14 . The U-shaped region is formed using a conventional shallow trench isolation (STI) process in a conventional CMOS process flow, ie shallow trenches 16 are formed and then filled with oxide 18 . The thickness of the silicon device layer 10 is thin enough that t...

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Abstract

A method of making a semiconductor device includes forming shallow trench isolation structures (14) in a semiconductor device layer. The shallow trench isolation structures are U- or O- shaped enclosing field regions( 28) formed of the semiconductor device layer which is doped and / or suicided to be conducting. The semiconductor device may include an extended drain region (50) or drift region and a drain region (42). An insulated gate (26) may be provided over the body region. A source region (34, 40) may be shaped to have a deep source region (40) and a shallow source region (34). A contact region (60) of the same conductivity type as the body may be provided adjacent to the deep source region (40). The body extends under the shallow source region (34) to contact the contact region (60).

Description

Technical field [0001] The present invention involves semiconductor devices and its production methods with field boards, which are particularly but not limited to field -based effects crystal tube (FET) with field boards. Background technique [0002] Many applications of semiconductor devices such as transistors need to be integrated with conventional logic circuits that can process components that can process high -voltage or large power power.In particular, this semiconductor device may require such semiconductor devices for power management and amplifying chips, display drivers and automotive applications. [0003] Typical land, this component requires 20 to 100V or even higher voltage.The device used can be reduced to reduce the surface (Resurf) device.These devices include field -effect transistor (FET) with regulating device, and adjustment devices such as field boards in adjacent drift areas to consume the drift zone during the cutter of the transistor.Essence [0004] ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/40H01L21/336H01L29/08H01L27/12H01L29/06H01L27/06H01L29/786
CPCH01L29/7816H01L29/0653H01L27/0617H01L29/7835H01L29/7824H01L29/0869H01L29/66659H01L29/786H01L29/66681H01L29/407
Inventor 简·雄斯基
Owner NXP BV
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