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Method for programming multi-order unit memory

A programming method and memory technology, applied in static memory, read-only memory, information storage, etc., can solve problems such as increasing bit error rate

Active Publication Date: 2010-10-13
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, as shown in FIG. 1C, after the first programming operation, some programming faster bits (indicated by the dashed area F) whose Vt value is close to but slightly lower than the PV value will be programmed again in the second programming operation up to Higher Vt values, thus causing the Vt distribution of the intended programmed state to become very wide, thereby increasing the bit error rate

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  • Method for programming multi-order unit memory
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  • Method for programming multi-order unit memory

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Embodiment Construction

[0013] The invention provides a programming method of an MLC memory. Memory bits that fail a predetermined programming state PV value are programmed using bit line bias BL. When at least one programming bit passes the PV value, the bias voltage BL decreases by a fixed value, and when no programming bit passes the PV value, the bias voltage BL increases by a fixed value. Then, use the new bias value BL to program the bits that fail the PV value. Therefore, the programming speed can be increased and the programming distribution can be narrowed to reduce the bit error rate of the memory.

[0014] Please refer to figure 2 , which shows a flowchart of a method for programming an MLC memory according to a preferred embodiment of the present invention. The MLC memory is, for example, a charge-trapped flash memory having an oxide-nitride-oxide (ONO) structure.

[0015] The MLC memory includes multiple storage units, such as 1024×256 storage units, and each storage unit has more t...

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Abstract

The invention relates to a programming method for an MLC memory. The MLC memory comprises a plurality of bits; each bit is provided with a plurality of programming states; and each programming state is provided with a programming verification (PV) value. The method comprises the following steps: (a) bit line voltage bias BL is used to program a bit in a memory with a threshold voltage (Vt) value less than a PV value in a preset programming state; (b) when the Vt values of all bits in the memory are not less than the PV value in the preset programming state, the method is finished; otherwise, the step (c) is continued; and (c) when the Vt values of all programming bits are less than the PV value, a formula BL=BL+K1 is set and the step (a) is repeated; when the Vt value of at least one programming bit is less than the PV value, a formula BL=BL-K2 is set and the step (a) is repeated, wherein K1 and K2 are fixed positive values.

Description

technical field [0001] The present invention relates to a programming method for a multi-level cell (multi-level cell; MLC) memory, and in particular to a programming method for an MLC memory that can obtain a narrower (tightened) programming distribution (program distribution) in a read operation method. Background technique [0002] Figure 1A to Figure 1D A schematic diagram showing the distribution of a threshold voltage (threshold voltage; Vt) when a programming bit reaches a predetermined programming state during a programming process of a conventional MLC memory is shown. Such as Figure 1A As shown, the memory initially has an erase-state Vt distribution, and each bit of the memory is programmed to a targeted program state. The Vt distribution of the predetermined program state has a program verify (PV) value (lower limit value). In order to make programming bits have a narrower Vt distribution, conventionally, a pre-program verification (Pre-PV) value is addition...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/10
Inventor 何信义邹年凯黄怡仁林永丰
Owner MACRONIX INT CO LTD