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Configurable single instruction multiple data unit

A multi-data and single-configuration technology, applied in the direction of single instruction multiple data multiprocessor, architecture with multiple processing units, electrical digital data processing, etc.

Active Publication Date: 2009-02-18
HONG KONG APPLIED SCI & TECH RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Unfortunately, the above Figure 1 to Figure 3 The SIMD unit constructs are restricted to reading and writing to a memory bank associated only with each PE
Additionally, each PE must execute the same instruction diff on the retrieved data

Method used

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  • Configurable single instruction multiple data unit
  • Configurable single instruction multiple data unit
  • Configurable single instruction multiple data unit

Examples

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Embodiment Construction

[0046] The method and apparatus for processing a Configurable Single Instruction Multiple Data (CSIMD) instruction are described below. In the following description, numerous specific details, including lookup table structures, indexes, pointers, etc., will be described. However, from this disclosure, those skilled in the art will appreciate that modifications and / or substitutions can be made without departing from the scope and spirit of the invention. In other instances, specific details may be omitted without obscuring the invention. Steps and / or features with the same or similar reference numbers in any one or more drawings, for the convenience of description, those steps and / or features have the same function or operation, unless the contrary situation occurs.

[0047] In the context of this specification, the word "comprising" has an open and non-exclusive meaning: "including in principle, but not necessarily exclusively", not "consisting of" or "consisting only of".

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Abstract

Methods and apparatuses for processing a Configurable Single-Instruction- Multiple-Data (CSiMD) instruction (500) are disclosed. In the method (600), a lookup table (LUT) (430) storing information is provided (610) to support random access of memory locations associated with a plurality of processing elements (PEs) (410) and to perform instruction variances by the PEs (410). A CSIMD instruction (500) is received (620), comprising a command (510) and ati index (520) to the lookup table (LUT) (430), to be executed by the PEs (410). The command of the received CSIMD instruction (500) is executed in parallel differently by the PEs (410) using the LUT index to randomly access the memory' locations.

Description

technical field [0001] The present invention relates generally to parallel processors and more particularly to single instruction multiple data (SIMD) processors. Background of the invention [0002] Parallel processing generally refers to the concept of increasing program execution speed by dividing a program into multiple program segments, which can be executed simultaneously by multiple processors. Depending on the type of application, different parallel processor configurations have different results and require different program segmentation. For example, a program can be divided into several parts, which can run simultaneously, and can run completely independently. This parallel processing is known as Multiple Input Stream, Multiple Output Stream (MIMD). This approach increases flexibility, but at the cost of increased complexity due to race conditions where timing discrepancy and data dependencies between processing elements of MIMD processors may Causes parts of a...

Claims

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Application Information

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IPC IPC(8): G06F15/80
CPCG06F15/8007G06F9/3004G06F9/3887G06F9/3885G06F9/383
Inventor 劳咏仪梅思行
Owner HONG KONG APPLIED SCI & TECH RES INST
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