Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Multiple die integrated circuit package

A technology of die and package, which is applied in the field of semiconductor device assembly and packaging, and can solve the problems of low cost, daily use and non-customized IC chips, etc.

Inactive Publication Date: 2009-03-11
TEXAS INSTR INC
View PDF0 Cites 7 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, many top packages are custom and often have a unique and limited footprint
Therefore, the top package cannot take advantage of low-cost, commodity, off-the-shelf IC chips that provide standard full-matrix footprint

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Multiple die integrated circuit package
  • Multiple die integrated circuit package
  • Multiple die integrated circuit package

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0012] [0009] Traditional tools and methods for manufacturing semiconductor devices with a PoP structure are limited by the constraints of the top package, the bottom package and their interfaces. These constraints can include a bottom package that is limited to one die, limited input / output (I / O) connections due to the perimeter matrix coverage area of ​​the top package, and customized (non-daily) more The use of expensive memory chips as top packages. This problem can be solved by using improved systems and methods for manufacturing semiconductor devices with PoP structures. According to one embodiment, in an improved system and method for manufacturing a semiconductor device having a PoP structure, a bottom layered substrate (BLS) is formed to include an interconnect pattern (IP) coupled to a plurality of conductive bumps (PCB) . The top substrate (TS) is formed by forming a polyimide tape (PT) pasted on the metal layer (ML) and a top die connected to the opposite side of the M...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
Thicknessaaaaaaaaaa
Heightaaaaaaaaaa
Login to View More

Abstract

In a method and system for fabricating a semiconductor device ( 100 ) having a package-on-package structure, a bottom laminate substrate ( 130 ) is formed to include interconnection patterns ( 170, 172 ) coupled to a plurality of conductive bumps (PCB) ( 130 ). A top substrate (TS) ( 140 ) is formed to mount a top package ( 110 ) by forming a polyimide tape (PT) ( 142 ) affixed to a metal layer (ML) ( 144 ), and a top die ( 136 ) attached to the ML ( 144 ) on an opposite side as the PT ( 142 ). A laminate window frame (LWF) ( 150 ), which may be a part of the BLS ( 130 ), is fabricated along a periphery of the BLS ( 130 ) to form a center cavity ( 160 ). The center cavity ( 160 ) enclosed by the BLS, the LWF and the TS houses the top die ( 136 ) affixed back-to-back to a bottom die ( 134 ) that is affixed to the BLS ( 130 ).

Description

Technical field [0001] [0001] The present invention generally relates to semiconductor device assembly and packaging; and, more specifically, to semiconductor devices having multiple dies in the same package structure. Background technique [0002] [0002] It is well known that consumers of next-generation electronic devices require more functions and features to be packaged in electronic devices that are smaller in size, consume less energy, and cost less than earlier generations. Semiconductor device manufacturers are responding by incorporating improved three-dimensional packaging technologies such as system-in-package (SiP), multi-chip packaging (MCP), stack-on-package (PoP) and similar other packaging technologies that provide integrated One or more dies and / or packages stacked vertically that operate as a semiconductor device. [0003] [0003] PoP generally includes two semiconductor packages stacked on top of each other, and can generally be used in products such as cellular...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L29/76
CPCH01L2924/14H01L2225/1058H01L25/105H01L2224/32145H01L2924/15331H01L2224/48472H01L2924/1433H01L2924/01087H01L2224/73265
Inventor K·P·赖恩
Owner TEXAS INSTR INC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com