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Variable delay circuit, delay time control method and unit circuit

A unit circuit and delay time technology, applied in the direction of automatic power control, electrical components, single output arrangement, etc., can solve problems such as delay time fluctuations

Inactive Publication Date: 2009-03-25
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However noise can generate fluctuations in delay time

Method used

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  • Variable delay circuit, delay time control method and unit circuit
  • Variable delay circuit, delay time control method and unit circuit
  • Variable delay circuit, delay time control method and unit circuit

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Embodiment approach

[0245] The present circuit is not limited to the above two embodiments, and various modifications can be made without departing from the subject matter.

[0246] For example, the memory controller 12 is not limited to the circuits described in the above embodiments, and various DDR3 memory interfaces in which the third variable delay circuit DWR can be mounted may be applied.

[0247] In the above embodiment, the third variable delay circuit DWR provided to each of SDRAM-1 to SDRAM-n is controlled so that the sum of the first delay time Dt1 and the second delay time Dt2 is fixed, however, this circuit It is not limited to this embodiment. For example, the first and second delay times Dt1 and Dt2 may be set as preset values ​​as long as their sum does not exceed the maximum delay time in the third variable delay circuit DWR.

[0248] In the above embodiment, a control signal for causing one of the plurality of unit circuits 31-1 to 31-10 to operate in the feedback operation mo...

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Abstract

The present invention relates to a variable delay circuit, a delay time control method and a unit circuit. The variable delay circuit constructed by connecting plural unit circuits in series which can change a delay time from input of signal until output of the signal by increasing or decreasing the number of unit circuits through which the signal concerned is passed. Each of the unit circuits is operable in a through operation mode in which a signal input from a unit circuit at the front stage is output to a unit circuit at the rear stage and also a signal input from a unit circuit at the rear stage is output to a unit circuit at the front stage and a feedback operation mode in which a signal input from a unit circuit at the front stage to a unit circuit at the front stage and a signal input from a unit circuit at the rear stage is output to a unit circuit at the rear stage.

Description

technical field [0001] This circuit relates to a technique of setting a delay time from the input time of a signal until the output time of a signal. Background technique [0002] Due to recent developments in storage interfaces, the speed of storage interfaces has increased year by year. One example is the DDR 3 (Double Data Rate 3) memory interface, etc., which is standardized in JEDEC (Joint Electron Device Engineering Council). [0003] When designing such a memory interface, a DLL (Delay Locked Loop) is indispensable. A variable delay circuit that can change the delay time from signal input to signal output is used in the DLL (for example, see JP-A-2005-286467). [0004] Means for realizing a variable delay circuit are roughly classified into an analog type and a digital type. Depending on the analog type, the delay time of the input signal is set in analog by varying the power supply voltage or circuit load in analog. On the other hand, depending on the digital typ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K5/13G11C7/10G11C11/407G11C11/4076H03K5/131H03K5/14
CPCH03K2005/00058G11C7/222H03L7/0814H03K5/133H03K5/135G11C7/22G11C11/407G11C11/4093G11C11/4096
Inventor 德广宣幸
Owner FUJITSU LTD