Method and apparatus for decoding, and encoding/decoding method
A technology of decoding and decoder, applied in the field of decoding
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Embodiment 1
[0066] In this embodiment, taking CRC-CCITT code as an error correction and detection application, 16 bits are calculated in parallel, and the number of bits N of the input packet can be divisible by 16 as an example, the error correction and detection method provided by the embodiment of the present invention is introduced. see Figure 4 , Figure 4 A schematic diagram of an implementation of a decoding method is provided for an embodiment of the present invention. Such as Figure 4 As shown, the generator polynomial of the CRC-CCITT code in the syndrome generating circuit is g(x)=x 16 +x 12 +x 5 +1; the anti-generator polynomial in the anti-generator polynomial circuit is g'(x)=g(x -1 )×x 16 =x 16 +x 11 +x 4 +1.
[0067] Such as Figure 4 As shown, when starting to work, the register in the syndrome generation circuit is cleared to 0, the gate 1 is opened, and the switch K is turned off. When a packet is input, the syndrome pattern s(x) is calculated, the gate 1 ...
Embodiment 2
[0118] In this embodiment, CRC-CCITT code is used as an error correction and detection application, 16 bits are calculated in parallel, and the number of bits N of the input packet is divisible by 16 as an example to introduce the error correction and detection method provided by the embodiment of the present invention. see Figure 5 , Figure 5 An implementation schematic diagram of yet another decoding method is provided for the embodiment of the present invention. Figure 5 The schematic diagram of the realization of the decoding method provided by the second embodiment of the present invention and Figure 4 The differences in the implementation schematic diagram of the decoding method provided by Embodiment 1 of the present invention are as follows: Figure 4 Input the received code polynomial from the lower bit of the syndrome generating circuit; Figure 5 Input the received code polynomial from the upper bit of the syndrome generating circuit. Such as Figure 5 As ...
Embodiment 3
[0172] see Figure 6 , Figure 6 A schematic structural diagram of a decoder provided by an embodiment of the present invention. Such as Figure 6 The shown decoder can specifically include:
[0173] The original syndrome generation unit 601 is configured to receive a code polynomial, calculate the modulo of the code polynomial to a preset generator polynomial, and obtain an original syndrome pattern.
[0174] The circuit unit 602 based on the inverse polynomial of the generator polynomial is used to receive and operate the original syndrome pattern, and the error polynomial corresponding to the original syndrome pattern is cyclically shifted to the low-order direction of the received code polynomial; determine the error pattern and output.
[0175] The buffer 603 is used to receive the code polynomial and output it.
[0176] The error correction unit 604 is configured to perform modulo two addition of the inverse order of the code polynomial output from the buffer and th...
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