Sram device with enhanced read/write operations

Abstract

An SRAM device includes: a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof; a second group of memory cells connected to a second local bit line and a second local complementary bit line for accessing data nodes thereof; and a global bit line and a global complementary bit line connected to the first and second local bit lines for accessing data nodes of the first and second groups of memory cells, wherein the first local bit line, the first local complementary bit line, the second local bit line, the second local complementary bit line, the global bit line and the global complementary bit line are constructed on a same metallization level in the SRAM device.

Description

technical field [0001] The present invention relates generally to integrated circuit design, and more particularly to a static random access memory (SRAM) with enhanced read / write operations. Background technique [0002] SRAM is a type of memory that can hold data as long as it is powered, without constantly refreshing it. figure 1 A circuit diagram 100 of a standard 6-tube SRAM cell with two cross-coupled inverters 102 and 104 is schematically shown. The inverter 102 includes a pull-up transistor 114 and a pull-down transistor 116 . The inverter 104 includes a pull-up transistor 118 and a pull-down transistor 120 . The first storage node 106 of the inverter 102 is directly connected to the gates of the two transistors of the inverter 104 . The second storage node 108 of the inverter 104 is directly connected to the gates of the two transistors of the inverter 102 . The first storage node 106 of the inverter 102 is written to and read from by a pass-gate transistor 110,...

AI Technical Summary

Problems solved by technology

[0005] A disadvantage of the existing SRAM device is: due to the relatively long interconnection path between the second metallization layer and the fourth metallization layer, which causes the RC effect, the pair of bit lines BL through the global bit line GBL and the global complementary bit line GBLB and complementary bit line BLB discharge (discharge) may be delayed

As a result, the performance of traditional SRAM devices is less than ideal, which provides room for further improvement of device performance

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