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Pre-decoding variable length instructions

A processor and pre-decoding technology, applied in instruction analysis, operation instruction conversion, electronic digital data processing, etc., can solve the problem of wasting I-cache storage space and so on

Inactive Publication Date: 2012-01-18
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Adding pre-decode bits to identify undefined base-length instructions can waste expensive I-cache storage space since undefined instructions are rarely encountered, and instructions longer than the base length have ample pre-decode bit encoding space

Method used

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  • Pre-decoding variable length instructions
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  • Pre-decoding variable length instructions

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Embodiment Construction

[0013] figure 1 is a functional block diagram of the processor 10. Processor 10 executes instructions in instruction execution pipeline 12 according to control logic 14 . Pipeline 12 may be a superscalar design, with multiple parallel pipelines, such as 12a and 12b. Each pipeline 12a, 12b includes various registers or latches 16 organized into pipe stages, and one or more arithmetic logic units (ALUs) 18 . Pipeline registers or latches 16 and ALU 18 may read operands from and / or write results to registers in general register file 28 .

[0014] The pipelines 12a, 12b fetch instructions from an instruction cache (I-Ccache or I$) 20 where memory addressing and grants are managed by an instruction-side translation lookaside buffer (ITLB) 22 . Data is accessed from a data cache (D-Cache or D$) 24 , where memory addressing and grants are managed by a main translation lookaside buffer (TLB) 26 . In various embodiments, ITLB 22 may include a copy of a portion of TLB 26 . Alternat...

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Abstract

A pre-decoder in a variable instruction length processor indicates properties of instructions in pre-decode bits stored in an instruction cache with the instructions. When all the encodings of pre-decode bits associate with one length instruction are defined, a property of an instruction of that length may be indicated by altering the instruction to emulate an instruction of a different length, and encoding the property in the pre-decode bits associated with instructions of the different length. One example of a property that may be so indicated is an undefined instruction.

Description

technical field [0001] The present invention relates generally to the field of processors and, in particular, to a method of predecoding variable length instructions to identify undefined instructions. Background technique [0002] Variable length instruction set architectures are known in the art. For example, when the Thumb (16-bit) extension is added to the ARM (32-bit) instruction set, the resulting mix can be viewed as a variable-length instruction set. As another example, executable Java code includes a series of bytecodes, where each instruction ranges between 2 and 256 bytes in length. In general, a variable length instruction set includes instructions having a base size and longer instructions that are integer multiples of the base size. [0003] Processor architectures and instruction sets have evolved over time. Specifically, as semiconductor technology advances, functionality that would otherwise require scalable software routines can be rendered in hardware. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30G06F9/318
CPCG06F9/382G06F9/3802G06F9/3017G06F9/30185G06F9/30174G06F9/30192G06F9/30152G06F9/30149G06F9/455G06F9/30G06F5/00
Inventor 罗德尼·韦恩·史密斯布赖恩·迈克尔·斯坦普尔
Owner QUALCOMM INC