Multi-product silicon wafer test method

Abstract

The invention discloses a method for testing a multi-product silicon chip. The steps are as follows: the minimum unit having regular arrangement in multi-product silicon chip test objects is found out; the coordinate positions of probes required to be manufactured by all the test objects in the unit are determined, the probes required by all the test objects are considered as a set; probe cards that simultaneously test the whole unit are manufactured; with the minimum unit as a unit, routes transversing the silicon chip are arranged, variety parameters are designed and completed; the positions of the tested objects are mapped, the test objects in the unit are transferred into regular arrangement supported by the a tester, corresponding relations between test results and the corresponding test objects are completed; the silicon chip is tested by means of Application simultaneous test, and the test results are mapped back to each original test objects; the test of multi-product silicon chip is finished. By the method, a plurality of multi-product test objects can be tested simultaneously, thus effectively improving the test efficiency of the multi-product silicon chip.

Description

technical field [0001] The invention relates to semiconductor testing technology, in particular to a multi-product silicon chip testing method. Background technique [0002] In the existing semiconductor field, on the one hand, products are diversified, and multi-product silicon wafers often appear, that is, there are several products on one silicon wafer at the same time; The layout on the screen is also more and more demanding, so even if it is the same product, the layout on the screen may become more diverse and complex. [0003] According to the traditional practice, when silicon wafers with this type of format appear, due to the irregular arrangement of the chips, the efficiency of the testing process in production will be severely reduced. It is mainly manifested in the following two aspects: one is that the arrangement of the tested objects is irregular, which brings difficulties in the expansion of the same test; Resulting in a significant reduction in test effici...

AI Technical Summary

Problems solved by technology

In this process, first, only a simple single test is performed, and the efficiency is reduced to 1 / N of the same test efficiency; second, the traversal path of the entire silicon chip is expanded to N times of the original, which brings a decrease in test efficiency

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