DRAM controller based on FPGA device

Abstract

The invention provides a dynamic random access memory (DRAM) controller based on a field programmable gate array (FPGA) device. The DRAM controller comprises an instruction state machine and a plurality of instruction decoders; when the DRAM controller starts to work, the instruction state machine generates an instruction code corresponding to each control instruction and transmits the instruction code to each instruction decoder through data wires, and the instruction decoder outputs a corresponding control instruction through output line of the control instruction, thereby fulfilling the control function of the DRAM, realizing the control over the DRAM device with high performance on the low level FPGA, and ensuring that the truth tables in the instruction decoders can be modified to facilitate the compatibility with the DRAM devices of different manufacturers.

Description

technical field [0001] The invention relates to a dynamic storage technology, in particular to a DRAM controller based on an FPGA device. Background technique [0002] Dynamic Random-Access Memory (Dynamic Random-Access Memory, referred to as DRAM) is a high-density memory. A Field Programmable Gate Array (Field Program Gate Array, FPGA for short) is a field programmable device, which contains a large number of Look-Up Table (LUT for short) modules. The FPGA-based DRAM controller is implemented using a finite state machine approach, such as figure 1 As shown, the output of all control lines is controlled by the state machine. When the existing conventional FPGA compiling tools layout and route the state machine module, because all the control lines are concentrated in the state machine, the use of local resources is too crowded, which affects the difficulty of the controller to achieve high performance. Especially when low-end FPGA devices are used to control high-perform...

AI Technical Summary

Problems solved by technology

When the existing conventional FPGA compiling tools layout and route the state machine module, because all the control lines are concentrated in the state machine, the use of local resources is too crowded, which affects the difficulty of the controller to achieve high performance. Especially when low-end FPGA devices are used to control high-performance DRAM devices, the performance bottleneck is more obvious

Moreover, for DRAM devices of different manufacturers or technologies, if the states of the control lines defined by the instructions are inconsistent, it is necessary to modify the layout and wiring of the FPGA device, and there is a certain risk.

How to overcome the performance bottleneck caused by the direct output of control commands by the DRAM controller has not been broken through in the industry

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