Optimization method and apparatus for verification vectors

An optimization method and a technology for optimizing devices, which are applied in the directions of measuring devices, measuring electricity, and measuring electrical variables, etc., can solve problems such as unsatisfactory simulation speed of simulation verification technology, inability to know the contribution of test programs, and redundancy of verification vectors, etc., to achieve Effects of shortening simulation time, accelerating verification convergence, and improving verification efficiency

CN101487876AActive Publication Date: 2009-07-22LOONGSON TECH CORP
0 Cites 8 Cited by

Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
Publication Date
2009-07-22

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
  • Figure 3
    Figure 3
Patent Text Reader

Abstract

The invention discloses an optimization method and a device for verifying a vector. The method comprises the following steps: according to the simulated initial verification vector, obtaining information on coverage rate of function points covered by the initial verification vector, initializing a list of the covered function points, and constructing a classification model; and sending a generated verification vector to the classification model, predicting the coverage rate of the function points covered by the generated verification vector, simulating the generated verification vector for improving the coverage rate of the function points, and updating the list of the function points according to the simulation result to obtain the verification vector with higher coverage rate. The method can reduce the number of the verification vector needing to be simulated, reduce the usage of the verification vector as much as possible and shorten simulation time, so as to improve verification efficiency and accelerate verification convergence.
Need to check novelty before this filing date? Find Prior Art

Description

technical field

[0001] The present invention relates to VLSI (Very Large Scale Integrated circuits, VLSI), design field, mainly relates to coverage evaluation technology in simulation verification, especially relates to verification vector optimization method and device. Background technique

[0002] With the wide application of integrated circuits, there are strict requirements on functional correctness, speed, power consumption, and reliability. Among them, functional correctness is the most basic requirement. The 2003 International Semiconductor Technology Development Report pointed out that verification has become the most expensive work in the integrated circuit design process. Verification is not only a hot spot in the research field, it is also directly related to the economic benefits of enterprises. Therefore, it is necessary to have an efficient verification design method to minimize the possibility of IC design errors, and at the same time shorten the time to ma...

Examples

Embodiment Construction

[0046] In order to make the purpose, technical solution and advantages of the present invention clearer, a verification vector optimization method and device of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0047]A verification vector optimization method and device of the present invention is to predict the coverage rate information of the newly generated verification vector according to the simulation information of the verified vector, and judge in advance whether it is possible to improve the current coverage rate. If it can be sent Enter the design to be verified to perform simulation operations, otherwise it is considered as a redundant verification vector and regenerated. It can reduce the use of verification vectors as much as possible an...