Optimization method and apparatus for verification vectors

Abstract

The invention discloses an optimization method and a device for verifying a vector. The method comprises the following steps: according to the simulated initial verification vector, obtaining information on coverage rate of function points covered by the initial verification vector, initializing a list of the covered function points, and constructing a classification model; and sending a generated verification vector to the classification model, predicting the coverage rate of the function points covered by the generated verification vector, simulating the generated verification vector for improving the coverage rate of the function points, and updating the list of the function points according to the simulation result to obtain the verification vector with higher coverage rate. The method can reduce the number of the verification vector needing to be simulated, reduce the usage of the verification vector as much as possible and shorten simulation time, so as to improve verification efficiency and accelerate verification convergence.

Description

technical field [0001] The present invention relates to VLSI (Very Large Scale Integrated circuits, VLSI), design field, mainly relates to coverage evaluation technology in simulation verification, especially relates to verification vector optimization method and device. Background technique [0002] With the wide application of integrated circuits, there are strict requirements on functional correctness, speed, power consumption, and reliability. Among them, functional correctness is the most basic requirement. The 2003 International Semiconductor Technology Development Report pointed out that verification has become the most expensive work in the integrated circuit design process. Verification is not only a hot spot in the research field, it is also directly related to the economic benefits of enterprises. Therefore, it is necessary to have an efficient verification design method to minimize the possibility of IC design errors, and at the same time shorten the time to ma...

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Problems solved by technology

However, when the simulation reaches a certain level, due to the complexity of the defined coverage space and some hard-to-reach states, the improvement of the coverage rate becomes very slow. At this time, a large number of test programs run are redundant. , and it is impossible to know the contribution of the test program to the improvement of the coverage rate before running the simulation, and a large amount of simulation time is spent on the verification of the covered function points, which is an important factor affecting the current verification efficiency

[0005] To sum up, the simulation speed of the existing simulation verification technology is unsatisfactory, and there is a large amount of redundancy in the verification vectors used

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