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Devices for processing video data

A technology of video data and equipment, which is applied in the field of video data processing, and can solve the problems of high chip gate count and different processing details

Inactive Publication Date: 2012-02-01
THOMSON LICENSING SA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the chip's gate count will be high: although the functional blocks for the different standards are similar, the processing details are different

Method used

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  • Devices for processing video data
  • Devices for processing video data
  • Devices for processing video data

Examples

Experimental program
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Embodiment Construction

[0020] The present invention uses a specific architecture and corresponding instruction set. The instruction set can be divided into two parts, namely macro-instructions similar to conventional RISC (Reduced Instruction Set Computer) instructions, and special-purpose instructions dedicated to video decoding. Macro instructions are mainly used to control the decoding process, and dedicated instructions are mainly used to handle calculations during the decoding process. Typically, instructions are 32 bits wide.

[0021] Instructions and video data to be processed are stored in SDRAMs. The architecture according to the invention uses a pipeline for instruction processing. Such as image 3 As shown, arbitrary instruction execution can be divided into the following five phases:

[0022] Instruction fetch (fetch): fetch instruction from SDRAM;

[0023] Decoding: translate the instruction format into an internal format;

[0024] Issue instruction (issue): issue an instruction t...

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Abstract

Video decoding includes very similar processing steps for different standards. The processing can work independently and in parallel in separate modules. Known multi-standard video decoders suffer from bottlenecks resulting from centrally organized processing. An improved apparatus for decoding video data comprises common elements of a RISC processor, including instruction providing unit (51,52,53, 54), queuing unit (55) and ALU (59), and special video processing modules, wherein the video processing modules are embedded in the RISC processor, so that they also receive instructions through the instruction bus (IB) and provide (IRB) data to the queuing unit (55), like the common RISC processor elements. The special video processing modules include a motion compensation unit (510), means (512) for performing IDCT and inverse quantization, an entropy decoding unit (513) and a filter unit (515).

Description

technical field [0001] The present invention relates to devices and methods for processing video data. In particular, this processing can be performed in the case of decoding video data. Background technique [0002] For today's video standards, such as MPEG2, AVS, VC-1, and H264, the decoding process mainly includes four stages: entropy or bitstream decoding, inverse transform and inverse quantization, motion compensation, and de-quantization. Blocking filter (de-blocking filter) (except MPEG2). In order to support high-resolution HD video, high-performance decoding processing is required. All current video standards use macroblocks (MBs), specifically 16x16 pixel MBs as luma processing units. A MB can be divided into 16 4×4 pixel sub-blocks. The corresponding color or chrominance data units (Cb and Cr) are 8x8 pixel blocks that can be divided into 16 2x2 pixel blocks. [0003] It is desirable to have a decoder chip that can handle all current standards. The tradition...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04N7/26H04N5/00
CPCH04N19/00781H04N9/804H04N21/44004H04N19/00533H04N7/26335H04N21/4382H04N7/50H04N19/00484H04N7/26707H04N19/423H04N19/44H04N19/61
Inventor 王识霖刘华平苑泽生
Owner THOMSON LICENSING SA