High-pressure level shift circuit with low power consumption

Abstract

The invention discloses a level shift circuit. The circuit consists of a first voltage switching stage (1), a second voltage switching stage (2) and a high-voltage output stage (3). The first voltage switching stage (1) and the second voltage switching stage (2) supply grid driving signals capable of being randomly adjusted according to the application to output-stage PMOS and NMOS transistors, so that the high-voltage output stage (3) can supply higher voltage and higher current for a load. The level shift circuit has higher switching speed, lower static power consumption, and smaller area. The level shift circuit can be applied to high-voltage driving chips for driving an electric motor, displaying a lithographic plate, driving a printer and the like, particularly applied to a high-low voltage compatible process with continually shrunk characteristic dimension and applied to high voltage and high current.

Description

technical field [0001] The invention is a level shift circuit for high and low voltage conversion, which is mainly used for power chip low voltage level conversion to high voltage level driving high voltage output stage to provide high voltage and large current for load. When working, the low voltage generally works below 5V (including 5V), while the high voltage can range from 5V to 100V, or even higher. The output stage transistor area is small, the conversion speed is fast, but the static power consumption is very low. Background technique [0002] With the rapid development of the semiconductor industry, the application fields of various power integrated chips continue to expand, such as the control of AC motors, the drive circuits of flat panel displays, etc. These drive chips all require level shift circuits. [0003] The CMOS high voltage output stage consists of a high voltage PMOS and NMOS transistors. The source of the PMOS tube is connected to the power supply, t...

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Problems solved by technology

[0004] However, there are many problems in the above-mentioned structure: firstly, because the gate of the NMOS transistor in the output stage is directly applied with a low-voltage control signal, the gate-source voltage of the NMOS transistor is very low, and the threshold of the high-voltage transistor is generally higher than that of the ordinary low-voltage transistor, so when When the NMOS tube is turned on, a large width-to-length ratio is required to generate a large output current

Secondly, since the voltage of the control signal on the gate of the PMOS transistor changes from 0 to VPP, this requires that the PMOS transistor can withstand all high voltages. In the high and low voltage compatible process, as the process size continues to shrink, the gate oxide thickness Constant thinning makes it difficult for PMOS tubes to meet reliability requirements

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