Two-port SRAM having improved write operation

Abstract

A two-port SRAM memory cell (20) includes a pair of cross-coupled inverters (40) coupled to storage nodes. An access transistor (54) is coupled between each storage node (SN, SNB) and a write bit line (WWB0) and controlled by a write word line (WWL0). The write word line is also coupled to a power supply terminal of the pair of cross-coupled inverters (40). During a write operation, the write word line is asserted. A voltage at the power supply terminal of the cross-coupled inverters (40) follows the write word line voltage, thus making it easier for the stored logic state at the storage nodes to change, if necessary. At the end of the write operation, the write word line is de-asserted, allowing the cross-coupled inverters (40) to function normally and hold the logic state of the storage node (SN). Coupling the power supply node of the cross-coupled inverters allows faster write operations without harming cell stability.

Description

technical field [0001] The present invention relates generally to memories and, in particular, to static random access memories (SRAMs) with improved write operations. Background technique [0002] Static Random Access Memory (SRAM) is commonly used in applications requiring high speed, such as memory in data processing systems. Each SRAM cell stores one bit of data and is implemented as a pair of cross-coupled inverters. SRAM cells are only stable at one of two possible voltage levels. The logic state of a cell is determined by whichever of the two inverter outputs is logic high, and can be caused to change state by applying a voltage of sufficient magnitude and duration to the appropriate cell input. The stability of SRAM cells is an important issue. SRAM cells must be stable against transients, process variations, soft errors, and power supply fluctuations that could cause the cell to change logic state unintentionally. Furthermore, ideally, an SRAM cell should provid...

AI Technical Summary

Problems solved by technology

Providing low-voltage SRAM with sufficient write margin and good cell stability can be difficult, often at the expense of degraded read and write performance

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