multi-bit memory device per cell

Abstract

The invention provides a per unit multi-bit storage device which comprises a storage cell array, a row address decoding module, a column address decoding module, a reading / writing control module, a plurality of first word lines and a plurality of first bit lines. According to the storage device disclosed by the invention, a semi-floating gate transistor with an embedded tunneling field-effect tube serves as a storage unit for data storage; on one hand, writing operation at relatively high speed can be realized through a band-to-band tunneling property of a tunneling diode, and on the other hand, threshold voltage of the transistor is controlled in a segmented manner, thus realizing per unit multi-bit storage.

Description

Technical field [0001] The present invention relates to the field of semiconductor devices, in particular to a multi-bit per cell storage device. Background technique [0002] The data stored in the random access memory (SRAM and DRAM) will be lost after the power is turned off, and it can only encode two data bits "0" and "1", which cannot achieve multi-bit storage per cell. Then people designed and combined In addition to the development of non-volatile memory, such as flash memory, it can not only store data when power is off, but also realize multi-bit encoding with high integration. [0003] The memory cell of the flash memory may include an electrically isolated floating gate, source and drain regions on the substrate on the first and second sides of the floating gate, and configured to control the floating gate The control gate. Typically, the threshold voltage of a memory cell of a flash memory depends on the amount of charge stored in the floating gate. The data stored ...

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Problems solved by technology

[0007] In view of the above-mentioned shortcoming of the prior art, the purpose of the present invention is to provide a multi-bit storage device per unit, which is used to solve the problem that the write operation speed of the multi-bit storage device in the prior art is relatively slow, and the write operation and the erasing operation require high voltage problem

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