Array basal plate of liquid crystal display device
A technology for a liquid crystal display device and an array substrate, which is applied in the field of array substrates, can solve the problems of not being able to release voltage in time, leaving afterimages on the screen, etc., and achieve the effects of improving anti-afterimage performance, improving efficiency, and improving quality.
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
no. 1 example
[0024] figure 1 It is a structural schematic diagram of the first embodiment of the present invention, figure 2 for figure 1 The enlarged schematic diagram of the region A in the middle, image 3 for figure 1 The square schematic diagram of area B in the center, such as Figure 1 ~ Figure 3 As shown, the thin film transistor liquid crystal display device includes an array substrate with several pixel units, and each pixel unit includes a first thin film transistor ( figure 1 A region in) and the second thin film transistor ( figure 1 The B area in); Wherein the source electrode 312 of the first thin film transistor and the source electrode 322 of the second thin film transistor are connected with the same data line 2, the drain electrode 311 of the first thin film transistor and the drain electrode 321 of the second thin film transistor are connected with The same pixel unit electrode is connected, and the gate 313 of the first thin film transistor is connected to the co...
no. 2 example
[0032] Figure 4 It is a schematic structural diagram of the second embodiment of the present invention, Figure 5 for Figure 4 The enlarged schematic diagram of the region A in the middle, Image 6 for Figure 4 The square schematic diagram of area B in the center, such as Figure 4 ~ Figure 6 As shown, the thin film transistor liquid crystal display device includes an array substrate with several pixel units, and each pixel unit includes a first thin film transistor ( Figure 4 A region in) and the second thin film transistor ( Figure 4 The B area in); Wherein the source electrode 312 of the first thin film transistor and the source electrode 322 of the second thin film transistor are connected with the same data line 2, the drain electrode 311 of the first thin film transistor and the drain electrode 321 of the second thin film transistor are connected with The same pixel unit electrode is connected, and the gate 313 of the first thin film transistor is connected to ...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 