Wafer alignment mark

Abstract

The invention provides a wafer alignment mark. In the prior art, the wafer edge is provided with a notch as a wafer alignment mark. The notch is easy to generate stress or defect on the wafer, thereby affecting the quality of the peripheral devices. In the invention, the wafer alignment mark is arranged at the wafer back and is an axis symmetry-type laser mark. The invention can effectively improve the finished product ratio of semiconductor devices on the wafer under the premise of ensuring the wafer alignment precision.

Description

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AI Technical Summary

Benefits of technology

This patented technology allows for better control over how well an integrated circuit (IC) device works when it's being manufactured onto its own wafers during production without any damage from misalignment between different layers that may occur due to imperfections such as cracks caused by external forces like pressure or impact force. By creating this alignmark at one side of each layer beforehand, there will be no risk of damaging these areas during subsequent processing steps. Overall, this new method helps improve productivity and quality more efficiently than previous methods.

Problems solved by technology

The present technology relates to improving the efficiency and precision with which wafers are processed by aligning them accurately without introducing any imperfections that could degrade their performance.

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