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Wafer alignment mark

A technology for aligning marks and wafers, applied in electrical components, electrical solid-state devices, circuits, etc., can solve problems such as defects or stress, affecting the quality and yield of semiconductor devices, and achieve the effect of improving yield

Inactive Publication Date: 2009-10-28
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This patented technology allows for better control over how well an integrated circuit (IC) device works when it's being manufactured onto its own wafers during production without any damage from misalignment between different layers that may occur due to imperfections such as cracks caused by external forces like pressure or impact force. By creating this alignmark at one side of each layer beforehand, there will be no risk of damaging these areas during subsequent processing steps. Overall, this new method helps improve productivity and quality more efficiently than previous methods.

Problems solved by technology

The present technology relates to improving the efficiency and precision with which wafers are processed by aligning them accurately without introducing any imperfections that could degrade their performance.

Method used

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Embodiment Construction

[0015] The wafer alignment mark of the present invention will be described in further detail below.

[0016] The wafer alignment mark of the present invention is disposed on the edge of the back surface 10 of the wafer 1 , and the wafer alignment mark is an axis-symmetric laser mark.

[0017] It should be noted that the surface opposite to the back surface 10 of the wafer 1 , that is, the front surface of the wafer 1 is used to manufacture semiconductor devices.

[0018] see figure 1 , In the first embodiment of the present invention, the wafer alignment mark 2 is disposed on the back surface 10 of the wafer 1, which is a laser mark and is a circle, and the diameter of the circle is 10 microns.

[0019] see figure 2 , In the second embodiment of the present invention, the wafer alignment mark 3 is disposed on the back surface 10 of the wafer 1 , which is a laser marking and is a cross.

[0020] see image 3 , in the third embodiment of the present invention, the wafer ali...

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PUM

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Abstract

The invention provides a wafer alignment mark. In the prior art, the wafer edge is provided with a notch as a wafer alignment mark. The notch is easy to generate stress or defect on the wafer, thereby affecting the quality of the peripheral devices. In the invention, the wafer alignment mark is arranged at the wafer back and is an axis symmetry-type laser mark. The invention can effectively improve the finished product ratio of semiconductor devices on the wafer under the premise of ensuring the wafer alignment precision.

Description

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Claims

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Application Information

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Owner SEMICON MFG INT (SHANGHAI) CORP