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Method and device for generating track record compression scheme of application program

A technology of application programs and compression schemes, applied in the field of heterogeneous multi-core architecture, can solve problems such as inapplicability of heterogeneous multi-core architecture

Inactive Publication Date: 2009-12-30
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, traditional online compression methods, such as zip and gzip, have code sizes of 77K and 64K, respectively, so such compression methods are not suitable for heterogeneous multi-core architectures

Method used

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  • Method and device for generating track record compression scheme of application program
  • Method and device for generating track record compression scheme of application program

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Embodiment Construction

[0023] It is believed that the above and other objects, features and advantages of the present invention will become more apparent through the following detailed description of specific embodiments of the present invention in conjunction with the accompanying drawings.

[0024] The inventors of the present invention have found through research that similarities exist between trace records of the same event. Generally, a trace record includes an event identifier and trace data, and several trace records examples of the same event are given below.

[0025] Track record 1:

[0026] 0000b00 1705 0200 0000 0016 0000 0000 0fff 3250

[0027] 0000b10 0000 0567 8aac dd28 0000 0567 8aac e2f1

[0028] 0000b20 0000 0000 1000 1abc 0000 0000 0000 0000

[0029] 0000b30 0000 0000 1026 c398 0000 0007 0fff 10c8

[0030] 0000b40 0000 0000 1001 31b4 0000 0030 ffff ffff

[0031] 0000b50 0000 0000 f7fd 0490 ffde f5b0 0000 0005

[0032] 0000b60 f7fc fff4 0000 8801 ffde f5e0 f7f1...

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Abstract

The invention relates to a method for generating a track record compression scheme of an application program, wherein the application program is operated on a heterogeneous multi-core system structure which comprises a main processor and a plurality of accelerators. The method comprises the following steps: operating at least a part of the application program on the heterogeneous multi-core system structure; collecting and analyzing track records which are generated by a plurality of the accelerators and comprise event identifiers and track data; and generating the track record compression scheme of the application program according to an analyzing result. The method can be applied to the heterogeneous multi-core system structure, and not only can compress the totally same track records, but also can compress the partially same track records by using a track record mode similar to the track records. Time for transmitting the track records can be shortened by compressing the track records of high-frequency events so as to reduce the influence on the behavior of the application program. The invention also discloses a device for generating the track record compression scheme of the application program, a method and a device for compressing the track records of the application program, and the heterogeneous multi-core system structure.

Description

technical field [0001] The present invention relates to application program debugging on a heterogeneous multi-core architecture, in particular to a method and device for compressing trace records generated when an application program is run on a heterogeneous multi-core architecture, and a heterogeneous multi-core device comprising the compression device Architecture. Background technique [0002] The heterogeneous multi-core architecture has obvious advantages in intensive computing and graphics processing. Generally, the heterogeneous multi-core architecture includes at least one main processor and multiple accelerators (also called "co-processors"), in which the main processing Accelerators are mainly used to distribute tasks and co-accelerators are used to perform specific calculation processing such as floating-point operations. An example of a heterogeneous multi-core architecture is the Cell Broadband Engine (CellBE) jointly developed by Sony, Toshiba and IBM, which...

Claims

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Application Information

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IPC IPC(8): G06F11/36
Inventor 李严王鲲冯宽杨雨东
Owner IBM CORP
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