Copper interconnection line with silicon through hole having high depth-to-width ratio and preparation method thereof
A high aspect ratio, through-silicon via technology, used in semiconductor/solid-state device manufacturing, ion implantation plating, overlay plating, etc., to solve problems such as difficulty in copper interconnects
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment Construction
[0033] see Figure 1 to Figure 4 , the high aspect ratio TSV copper interconnection wire of the present invention is: one end of the copper interconnection wire is thicker and the other end is thinner, and the end close to the conductive silicon wafer is a thin end.
[0034] The first embodiment of the manufacturing process of the above-mentioned high-aspect-ratio through-silicon via copper interconnection line mainly includes the following steps:
[0035] 1. Prepare a through-hole mask on the surface of the silicon wafer by photolithography;
[0036] 2. Using Inductively Coupled Plasma (ICP) Deep Reactive Ion Etching (DRIE) technology to obtain gradually thinner through-silicon holes on silicon wafers to make device silicon wafers, including the following processes;
[0037] (a) Etching on the front side of the silicon wafer to form a blind hole with a gradually changing diameter at the thick inner end of the opening and meeting the aspect ratio requirements;
[0038] (b) E...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 