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Copper interconnection line with silicon through hole having high depth-to-width ratio and preparation method thereof

A high aspect ratio, through-silicon via technology, used in semiconductor/solid-state device manufacturing, ion implantation plating, overlay plating, etc., to solve problems such as difficulty in copper interconnects

Inactive Publication Date: 2014-04-09
GUANGZHOU HKUST FOK YING TUNG RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In addition, it is still difficult to prepare defect-free copper interconnect lines with an aspect ratio of about 15 by electrodeposition process

Method used

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  • Copper interconnection line with silicon through hole having high depth-to-width ratio and preparation method thereof
  • Copper interconnection line with silicon through hole having high depth-to-width ratio and preparation method thereof
  • Copper interconnection line with silicon through hole having high depth-to-width ratio and preparation method thereof

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Embodiment Construction

[0033] see Figure 1 to Figure 4 , the high aspect ratio TSV copper interconnection wire of the present invention is: one end of the copper interconnection wire is thicker and the other end is thinner, and the end close to the conductive silicon wafer is a thin end.

[0034] The first embodiment of the manufacturing process of the above-mentioned high-aspect-ratio through-silicon via copper interconnection line mainly includes the following steps:

[0035] 1. Prepare a through-hole mask on the surface of the silicon wafer by photolithography;

[0036] 2. Using Inductively Coupled Plasma (ICP) Deep Reactive Ion Etching (DRIE) technology to obtain gradually thinner through-silicon holes on silicon wafers to make device silicon wafers, including the following processes;

[0037] (a) Etching on the front side of the silicon wafer to form a blind hole with a gradually changing diameter at the thick inner end of the opening and meeting the aspect ratio requirements;

[0038] (b) E...

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Abstract

The invention relates to a copper interconnection line with a silicon through hole having a high depth-to-width ratio, which is a copper interconnection line, the diameter of which is larger and larger from a starting end to a finishing end of the electrodeposited copper. The method for preparing the copper interconnection line by adopting the electrodeposition is characterized in that the electrodeposited copper grows from a thinner end to a thicker end; an anode adopts a high-purity electrolytic copper plate, the area of which is larger than or equal to two times of that of a cathode; the conducting current density is kept constant; in the transitional electrodeposited process, the intensities of the forward current and the reverse current are equal; and the conducting time of the forward current is 5 times of that of the reverse current. The invention uses the silicon through hole which is gradually thinned as a channel for growing the electrodeposited copper, and the silicon through hole can automatically adjust the distribution of local effective current densities in the electrodeposited process and is beneficial to enabling air bubbles generated by the cathode in the electrodeposited process to escape from the silicon through hole, thereby realizing the preparation of the copper interconnection line with the silicon through hole having the high depth-to-width ratio and no hole defects.

Description

technical field [0001] The invention relates to a vertical copper connection line through a silicon hole with a high aspect ratio of an integrated circuit, and also relates to a method for preparing the vertical copper connection line by adopting a diverting electrodeposition technology. Background technique [0002] In addition to improving the interconnection density and high-speed signal transmission characteristics, through-silicon via interconnection technology can also reduce power loss by reducing the length of the entire lead. At the same time, the contact hole also provides a cooling channel for the Joule heat emitted by the die. So as to provide a better solution for the three-dimensional integration of MEMS packaging and IC. However, through-silicon via interconnection technology still faces technical challenges such as the production of smaller through-holes, defect-free metallization in through-holes, and the formation of electrical insulation between interconne...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/528H01L21/768C23C14/34C23C14/16C25D7/06C25D5/18C23F1/12C23C28/02
Inventor 谷长栋徐辉张统一
Owner GUANGZHOU HKUST FOK YING TUNG RES INST