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Integrated circuit and its power management method

A technology of integrated circuits and transistors, applied in the field of systems that provide negative voltage, to achieve the effect of reducing complexity

Active Publication Date: 2016-12-14
CONVERSANT INTPROP MANAGEMENT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] However, as components range in device size from 250nm to 130nm or below, the current consumption of the device in standby mode (also known as static leakage) becomes a growing part of the integrated circuit power budget

Method used

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  • Integrated circuit and its power management method
  • Integrated circuit and its power management method
  • Integrated circuit and its power management method

Examples

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Embodiment Construction

[0024] As shown in the exemplary figures (where like reference numerals indicate like or corresponding elements in the figures), exemplary embodiments of systems and methods according to the present invention are described in detail below. However, it should be understood that the present invention can be implemented in various forms. For example, while minimizing static leakage of integrated circuits has been described herein, the aspects of the invention may also be implemented on circuits that are not contained within integrated circuits. Therefore, specific description disclosed herein is not to be interpreted as limiting, but as a basis for the claims and as a basis for teaching those skilled in the art to practice the invention in any suitably embodied system, structure, method, process or manner. representative basis.

[0025] figure 1 is a block diagram of an integrated circuit 100 implementing a system for minimizing static leakage according to one embodiment of the...

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Abstract

The present invention provides an integrated circuit and a power management method thereof. The integrated circuit includes: two power supply terminals configured to supply power to the integrated circuit, the power supply terminal includes a positive power supply terminal and a ground terminal, the voltage (VDD) of the positive power supply terminal and the Voltage (VSS) jointly defines the range of the logic level; logic unit, the logic unit is selected from one of the logic gate and the storage unit, and the logic unit includes a sleep transistor, and the sleep transistor is connected in series with one of the power supply terminals; the voltage generator , configured to selectively generate a voltage outside the range of logic levels; a circuit configured to supply a voltage outside the range of logic levels to the sleep transistor during the power saving mode; and a voltage regulator configured to , the voltage generator is controlled to substantially reduce leakage current through the sleep transistor, and the voltage regulator includes an analog sleep transistor. The invention can minimize the static leakage and reduce the complexity of the integrated circuit manufacturing process.

Description

[0001] The present invention is a divisional application of an invention patent application with the filing date of July 5, 2005, the application number of 200580026872.4, and the title of the invention "system and method for minimizing static leakage of integrated circuits". [0002] Cross References to Related Applications [0003] This application requires the title "Systems and Methods for I / O and Power Island Management and Leakage Control on Integrated Circuits" filed on July 9, 2004 Priority of U.S. Provisional Patent Application No. 60 / 586,565, which is hereby incorporated by reference. This application is also related to U.S. Patent Application No. 10 / 840,893, entitled "Managing Power on Integrated Circuits Using Power Islands," filed May 7, 2004, which is incorporated herein by reference . technical field [0004] The present invention relates generally to integrated circuits, and more particularly to systems and methods for providing negative voltages in integrate...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/00
Inventor 兰迪·卡普兰史蒂文·施瓦克
Owner CONVERSANT INTPROP MANAGEMENT INC
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