Method for reducing current on bonded leads of power supply pads of chip

A technology of power supply pads and bonding wires, applied in circuits, electrical components, electrical solid devices, etc., can solve problems such as excessive current, and achieve the effects of easier implementation, reduced noise, and reduced current

Active Publication Date: 2010-04-21
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] In order to solve the problem in the prior art that the current on the bonding wire connecting the power supply pad and the lead frame is too large to cause synchronous conversion output, the present invention provides a bonding wire that does not increase the chip area and can reduce the power supply pad method of current on

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  • Method for reducing current on bonded leads of power supply pads of chip
  • Method for reducing current on bonded leads of power supply pads of chip
  • Method for reducing current on bonded leads of power supply pads of chip

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Embodiment Construction

[0017] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0018] First, please refer to figure 2 , figure 2 It is a schematic flow chart of a method for reducing the current on the bonding wire of the chip power supply pad in the present invention, from figure 2 It can be seen that the present invention includes the following steps: Step 21: set a plurality of power supply pads on the chip, and the power supply pads are rectangular, octagonal or circular; Step 22: set a plurality of power pads at the four corners of the chip A dummy pad for alleviating chip stress, the dummy pad is rectangular, octagonal or circular; step 23: both the power pad and the dummy pad are connected to the power bus, and the power pad and The dummy pad is electrically connected to the lead frame through a bonding wire, the diameter of the bonding wire is in the range of 25 μm to 75 μm, and the power pad and th...

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PUM

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Abstract

The invention provides a method for reducing current on bonded leads of power supply pads of a chip. The chip is provided with a plurality of power supply pads and a plurality of virtual pads which are arranged at four corners of the chip and used for relieving chip stress; and the power supply pads and the virtual pads are all connected with a power bus and are electrically connected with a lead frame through the bonded leads. The method reduces the current on each bonded lead so as to reduce inductance on each bonded lead and noise caused by the inductance; and the whole bonding process is easy to implement, and an extra area of the chip is not occupied.

Description

technical field [0001] The invention belongs to a semiconductor technology, in particular to a method for reducing the current on the chip power pad bonding wire. Background technique [0002] After the silicon wafer has passed the electrical test, the assembly and packaging of individual chips begins. In the traditional process, the final assembly of integrated circuits separates each good chip from the silicon wafer and pastes the chip on a metal lead frame or package. For lead frame assembly, thin wires are used to interconnect the metal pads on the surface of the chip to the inner ends of the lead frame that provide access to the chip points. [0003] In the modern era that is more and more fastidious, data processing tends to be ultra-high frequency, and the system environment with higher and higher input / output (I / O) operating rates is also relatively developed, making simultaneous switching output (SSO) a An important topic, this problem is also very obvious in the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/60H01L23/482H01L23/488
CPCH01L2224/48092H01L2224/49113H01L2924/30107H01L2224/45147H01L2224/45015H01L2224/45124
Inventor 何军
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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