Multi-point silicon transistor with double ultra sallow isolation structures

Abstract

The invention discloses a multi-point silicon transistor with double ultra sallow isolation structures, comprising at least two adjacent transistor units. Each transistor unit is respectively and horizontally arranged in a silicon substrate and the adjacent transistor units are symmetrically arranged; each transistor unit comprises a first ultra shallow channel structure, a second ultra shallow channel structure, a first type doped zone, a second type doped zone and a second type light doped zone arranged between the first type doped zone and the second type doped zone. The first type doped zone and the second type doped zone are not only adjacent to the first ultra shallow channel structure and the second ultra shallow channel structure, but also adjacent to the second light doped zone. In addition, a first type emitter structure is formed on the surface of the second light doped zone. The invention can ensure that the internal resistance of a base electrode connecting lead connectedwith a base electrode is reduced so as to reduce the power consumption of the entire device.

Description

technical field [0001] The invention relates to a transistor, in particular to a multi-point silicon transistor with a double ultra-shallow isolation structure. Background technique [0002] General metal oxide semiconductor (MOS) devices have been widely used in the design and manufacture of integrated circuits (IC) due to their low power consumption and high integration characteristics. However, MOS devices and bipolar transistors (BJT ) devices are inferior to BJT devices in terms of withstand voltage, operating speed, and current driving force. Therefore, in some IC applications that emphasize high speed, high withstand voltage, high current drive and analog circuits, most of them still use BJT devices, such as power transistor ICs, power electronic switch IC devices, etc. [0003] figure 1 and figure 2 Respectively, the structural cross-sectional view and the structural top view of the multi-point NPN type BJT device in the prior art. The multi-point BJT device is m...

AI Technical Summary

Problems solved by technology

Taking the first transistor unit 18 as an example, because the way the carriers flow will affect the electrical properties of the entire device, in the aforementioned existing transistor unit structure, when the carriers move from the first P-type doped region 182 When entering the base, because the adjacent surface of the first P-type doped region 182 and the first P-type lightly doped region 183 is too large, the base resistance is too large, and the current driving capability of the entire device cannot be further improved.

In addition, for the interface between the first N-type doped region 181 and the first P-type lightly doped region 183, since the current here is relatively large, the breakdown voltage here is relatively low, and the avalanche effect is likely to occur.

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