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Clock domain crossing timing simulation system and method

A technology that crosses the clock domain and simulates the system. It is applied in the computer field and can solve problems such as unfavorable reaction to the real situation of the system and the inability of the simulation to continue correctly.

Active Publication Date: 2010-05-26
LOONGSON TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

A synchronizer is used at the interface of different clock domains to connect signals from two different clock domains. The registers used in the synchronization process of signals in different clock domains will enter a metastable state because the setup time or hold time is not satisfied. In reality The synchronizer has the function of eliminating this metastable state, but in the timing simulation, this metastable state will be transferred to the subsequent registers, so that the simulation cannot continue to proceed correctly, so it is necessary to propose a cross-clock domain timing simulation device with method
[0003] In the timing simulation of existing cross-clock domain systems, most of them use the same clock to simulate the system to avoid the problem of multiple clock domains. The disadvantage is that it is not conducive to reflecting the real situation of the system

Method used

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  • Clock domain crossing timing simulation system and method

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Embodiment 1

[0037] see figure 1 , The invention discloses a timing simulation system across clock domains, the system includes a finder, a modifier and a simulator.

[0038] 【Finder】

[0039] The finder is used to confirm that all the hierarchical paths of the cross-clock domain registers can be searched in the timing reverse labeling file, otherwise, the hierarchical path of the cross-clock domain register corresponding in the cross-clock domain register hierarchical path list is corrected according to the netlist; Then, the position of the cross-clock domain register (all the cross-clock domain registers in the hierarchical path list) is searched in the timing back-annotation file, and the position of the cross-clock domain register is output to the modifier.

[0040] The search process of the finder is: list the register hierarchy path across the clock domain, and the finder searches the cross-clock domain register in the hierarchical path list in the timing back-annotation file; if not...

Embodiment 2

[0067] see figure 1 , Figure 4 , this example combines figure 1 The timing simulation system and simulation method across clock domains of the present invention are introduced.

[0068] like figure 1 As shown, the input of the finder 103 is the cross-clock domain register hierarchical path list 101 and the timing anti-annotation file 102 containing delay information, and the finder 103 checks whether the cross-clock domain register hierarchical path list 101 exists in the timing anti-annotation file containing delay information. In the marking file 102, if the cross-clock domain register hierarchical path list 101 contains entries that do not exist in the timing reverse marking file 102, it is necessary to correct the corresponding cross-clock domain register in the cross-clock domain register hierarchical path list according to the netlist. Hierarchical path; if the entries in the cross-clock domain register hierarchy path list 101 can be found in the timing anti-annotati...

Embodiment 3

[0073] In this embodiment, there is a netlist including a cross-clock domain design and a corresponding timing anti-annotation file, and timing simulation needs to be performed on the netlist.

[0074] First point out the cross-clock domain registers in the design, which are given in the form of hierarchical paths, and search for these cross-clock domain registers in the timing back-annotation file. If they cannot be found, correct the hierarchical path list of the cross-clock domain registers according to the netlist The hierarchical path of the corresponding cross-clock domain register in the list, until all the cross-clock domain registers in the hierarchical path list of the cross-clock domain register can be found in the timing back-annotation file; if all the hierarchical paths of the cross-clock domain register can be If it is found in the timing anti-annotation file, the next step is processed on the timing anti-annotation file, and the position of the cross-clock domai...

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Abstract

The invention discloses clock domain crossing timing simulation system and method. The clock domain crossing timing simulation system comprises a finder, a modifier, and a simulator. In the clock domain crossing timing simulation method, the finder confirms that all clock domain crossing registers on a hierarchical path list can be found and obtained in timing annotation files; then positions of the clock domain crossing registers are found in the timing annotation files and are output to the modifier; the modifier receives the positions of the clock domain crossing registers in the timing annotation files, which are sent by the finder, eliminates timing annotation information of the clock domain crossing registers in the timing annotation files, and outputs the processed timing annotation files to the simulator; and the simulator is used for simulating timing information annotation back net lists in the timing annotation files. Through processing delayed annotation information, the invention achieves that indefinite states occurring in a cross clock domain part in simulation are eliminated, enables a system with a plurality of clock domains to be capable of timing simulation, and is more capable of reflecting true situations of the plurality of clock domain systems compared with other methods.

Description

technical field [0001] The invention belongs to the technical field of computers, and relates to a timing simulation system, in particular to a timing simulation system crossing clock domains; in addition, the invention also relates to a simulation method of the timing simulation system crossing clock domains. Background technique [0002] Digital electronic systems such as computer systems often need to use multiple different clock domains. A synchronizer is used at the interface of different clock domains to connect signals from two different clock domains. The registers used in the synchronization process of signals in different clock domains will enter a metastable state because the setup time or hold time is not satisfied. In reality The synchronizer has the function of eliminating this metastable state, but in the timing simulation, this metastable state will be transferred to the subsequent registers, so that the simulation cannot continue to proceed correctly, so it ...

Claims

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Application Information

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IPC IPC(8): G06F1/04
Inventor 李祖松杨耀武汪文祥
Owner LOONGSON TECH CORP
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