Dynamic squelch detection power control

Abstract

In one embodiment, the present invention includes power control logic for squelch detection circuitry to enable selective enabling of one or more squelch detection circuits of an interconnect interface in a low power mode. The logic may include a squelch mode control register to select a first mode or a second mode of power control, a second register coupled to the squelch mode control register to receive software settings to indicate which squelch detect circuit(s) to disable in a low power state of the interconnect, and a detector to dynamically detect a logical lane zero of the interconnect in the second mode. Other embodiments are described and claimed.

Description

technical field [0001] The present invention relates to dynamic squelch detection power control. Background technique [0002] Modern computer systems are often formed of many semiconductor components that can communicate together via various interconnects such as those found on circuit boards. A common such interconnection mechanism used, for example, for incorporation into peripheral devices such as graphics cards is based on the PCIExpress TM Specification Base Specification Version 2.0 (released on January 17, 2007) (hereinafter referred to as PCIe TM specification) of the link Peripheral Component Interconnect Express (PCIe TM )protocol. Such interconnects can be formed from multiple layers including transaction layer, link layer and physical layer. [0003] To reduce power consumption when no communication occurs on a given interconnect, various mechanisms may be provided. If communication is not likely to occur for a period of time, the interconnect may be placed...

AI Technical Summary

Problems solved by technology

However, since squelch logic is usually provided for each lane of the interconnect, such squelch logic consumes a lot of power

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