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Method for manufacturing insulation layer and method for manufacturing semiconductor device using the insulation layer

A technology on the insulating layer and on the insulating layer, which is applied in the direction of semiconductor/solid-state device manufacturing, coating, electrical components, etc., and can solve problems such as contact failure

Inactive Publication Date: 2013-03-20
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, in the process of forming the contact hole 109 for the landing plug, the nitride layer 108 remains on the substrate 101, which causes a contact-not-open phenomenon.

Method used

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  • Method for manufacturing insulation layer and method for manufacturing semiconductor device using the insulation layer
  • Method for manufacturing insulation layer and method for manufacturing semiconductor device using the insulation layer
  • Method for manufacturing insulation layer and method for manufacturing semiconductor device using the insulation layer

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Experimental program
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Embodiment approach

[0029] Figure 3A-3D is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment.

[0030] refer to Figure 3A , a plurality of patterns 12 with certain gaps are formed on the substrate 11 in which the predetermined structure is formed. The pattern 12 may include, for example, gates, bit lines, and metal lines.

[0031] A nitride layer 13 is formed on the resulting structure including pattern 12 . The nitride layer 13 prevents impurities included in the interlayer dielectric layer from entering the substrate 11 or the pattern 12 in a subsequent process of forming the interlayer dielectric layer. The nitride layer 13 can be made of silicon nitride (Si 3 N 4 )form.

[0032] The deposition thickness of the nitride layer 13 may be adjusted in consideration of the gap filling characteristics of the interlayer dielectric layer in the subsequent process of forming the interlayer dielectric layer and the loss thickness of the...

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Abstract

A method for fabricating an insulation layer includes forming an insulation layer over a nitride layer using a silicon source and a phosphorus source, wherein the insulation layer includes a first insulation layer contacting the nitride layer and a second insulation layer formed on the first insulation layer, wherein the first insulation layer is formed using a higher flow rate of the silicon source and a lower flow rate of the phosphorus source than used with the second insulation layer.

Description

[0001] related application [0002] This application claims priority from Korean Patent Application No. 10-2008-0127723 filed on December 16, 2008, the entire contents of which are incorporated herein by reference. technical field [0003] The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing an insulating layer capable of preventing loss of a nitride layer due to a phosphorus-containing insulating layer, and to a method of manufacturing a semiconductor device using the insulating layer. Background technique [0004] As semiconductor devices become more highly integrated, circuit pattern sizes / dimensions decrease and aspect ratios between patterns increase. Therefore, the tolerance of the gap-fill process is reduced. Therefore, an insulating layer having proper reflow characteristics such as borophosphosilicate glass (BPSG) is used as an interlayer dielectric layer filling the gaps between patterns. If...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/31H01L21/3105C23C16/52H01L21/336
CPCH01L21/31625H01L21/76828H01L21/31051H01L21/76834H01L21/02271H01L21/02129H01L21/022H01L21/76837H01L21/31H01L21/20H01L21/324
Inventor 尹良汉
Owner SK HYNIX INC