Silicon-based lateral double-diffused metal-oxide semiconductor device on insulating substrate

Abstract

The invention relates to a SOI-based lateral double-diffused metal-oxide semiconductor (LDMOS) device. Aimed at the problem that only part of the drift region in the prior SOI-based LDMOS device takes part in electric conduction, the invention discloses the SOI-based lateral double-diffused metal-oxide semiconductor device, which utilizes n-type dopant bars and p-type dopant bars in the drift region to conduct electricity together, consequently, the drift region is sufficiently utilized, the conduction loss is reduced, and the performance of the device is improved. In the technical scheme, ann well is arranged in a drain electrode, a drain p plus contact region and a drain n plus contact region are arranged in the n well of the drain electrode, the parasitic PNP transistor is adopted to ensure that the n-type dopant bars and the p-type dopant bars in the drift region can take part in electric conduction together, consequently, the requirement of a power integrated circuit on low resistance can be met, the device can withstand the voltage of 200V to 700V, the device can be used in a high-voltage level shift unit, and the level shift unit can be applied in a PDP addressing integrated circuit to serve as an active element.

Description

technical field [0001] The invention relates to an SOI (Sillicon-On-Insulator, silicon on an insulating substrate)-based integrated circuit, in particular to a lateral double-diffused metal oxide semiconductor (LDMOS) device on an SOI-based. Background technique [0002] SOI technology introduces a buried oxide layer between the top silicon and the substrate. It can realize the dielectric isolation of the components in the integrated circuit, and completely eliminate the parasitic latch effect in the bulk silicon CMOS circuit. Integrated circuits made of SOI materials also have the characteristics of small parasitic capacitance, high integration density, fast device speed, simple manufacturing process, and small short-channel effect, and are especially suitable for low-voltage and low-power circuits. [0003] The LDMOS device integrated on the SOI material is completely isolated from the low-voltage logic circuit by dielectric, and it is beneficial to avoid the latch-up eff...

AI Technical Summary

Problems solved by technology

[0006] The technical problem to be solved by the present invention is to provide an SOI-based lateral double-diffused metal oxide semiconductor device, which utilizes n-type impurity strips in the drift region and The p-type impurity strips are jointly conductive to fully utilize the drift region, reduce conduction loss, and improve device performance

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