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A circuit for reducing CMOS transient power consumption

A technology of transient power consumption and MOS transistors, which is applied in the field of micro-nano electronics and can solve problems such as deviations in simulation results

Active Publication Date: 2011-12-21
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

But since the bias current used is only 100nA
According to theory, the transient current should be kept constant at around 100nA, but the simulation results deviate greatly from the theory

Method used

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  • A circuit for reducing CMOS transient power consumption
  • A circuit for reducing CMOS transient power consumption
  • A circuit for reducing CMOS transient power consumption

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Embodiment Construction

[0017] The specific implementation manner of the present invention will be further described below by taking a traditional CMOS gate circuit-inverter as an example in conjunction with the accompanying drawings.

[0018] Please see image 3 A circuit for reducing CMOS transient power consumption of the present invention includes a CMOS inverter formed by connecting a PMOS transistor P1 and an NMOS transistor N1. The PMOS transistor used is provided with a source, a drain, a gate and a base drawn out from its substrate common well (N well). The gate of the PMOS transistor P1 is connected to the gate of the NMOS transistor N1 and is an input terminal; the drain of the PMOS transistor P1 is connected to the source of the NMOS transistor N1 and is an output terminal; the source of the PMOS transistor P1 is connected to a high level , that is, the power supply level is connected; the drain of the NMOS transistor N1 is grounded.

[0019] In order to limit the transient current of t...

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Abstract

The invention relates to a circuit for reducing the transient power consumption of CMOS, which comprises a CMOS gate circuit formed by connecting a PMOS transistor and an NMOS transistor, the source of the PMOS transistor is connected to a power supply level; An isolation device is connected between the base of the transistor and the power supply, so that the base is isolated from the power supply. At the same time, a voltage stabilizing device is added to the base to keep the base voltage constant within a certain range. Therefore, in the process of switching the input signal of the gate circuit, no feed-through current will be caused from the power supply to the input terminal through the base, thereby reducing the transient power consumption of the CMOS integrated circuit, and due to the existence of the voltage stabilizing device, it is guaranteed The base potential is always constant and does not affect logic gate operation.

Description

technical field [0001] The invention relates to a CMOS integrated circuit, in particular to a circuit for reducing the transient power consumption of the CMOS integrated circuit. The invention belongs to the technical field of micro-nano electronics. Background technique [0002] There are two main sources of power consumption for ordinary CMOS gate circuits: one is called static power consumption; the other is dynamic power consumption. Static power consumption refers to the power consumption caused by the leakage current from the power supply terminal to the ground when the input terminal of the CMOS gate circuit is kept constant. Dynamic power consumption refers to the power consumption caused by the instantaneous change of the input terminal of the CMOS gate circuit. When the input terminal of the CMOS gate circuit changes, the pull-up network and the pull-down network of the gate circuit must be turned on at the same time, causing a large transient current to flow fro...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/20
Inventor 丁晟宋志棠陈后鹏
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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