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Testing structure of integrity of semiconductor device gate oxide

A technology of gate oxide layer and test structure, which is applied in the field of test structure of semiconductor device gate oxide layer integrity, can solve problems such as device failure, and achieve the effect of avoiding negative effects

Active Publication Date: 2014-03-12
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] The present invention aims to solve the problem that the gate oxide layer integrity test structure in the prior art ignores the defects near the edge of the gate oxide layer and the edge of the shallow trench isolation, which causes the device to fail due to defects in this part.

Method used

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  • Testing structure of integrity of semiconductor device gate oxide
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  • Testing structure of integrity of semiconductor device gate oxide

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Embodiment Construction

[0022] In order to make the technical features of the present invention more comprehensible, specific embodiments are given below in conjunction with the accompanying drawings to further describe the present invention.

[0023] An embodiment of the present invention provides a test structure for the integrity of a gate oxide layer of a semiconductor device. The test structure includes: an active region; the plurality of shallow trench isolations (STIs) are arranged in parallel in the active region; The plurality of gate structures cover the shallow trench isolation in parallel and at intervals.

[0024] Wherein the gate structure includes: a gate and a gate oxide layer. The gate is polysilicon or metal gate. The gate oxide layer is an oxide layer, a nitride layer or a high dielectric constant material layer.

[0025] In an embodiment of the present invention, the plurality of gate structures and the plurality of shallow trench isolations are arranged in parallel.

[0026] S...

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Abstract

The invention discloses a testing structure of the integrity of a semiconductor device gate oxide, comprising an active area, wherein a plurality of shallow slot isolations are arranged in the active area in parallel at intervals, and a plurality of gate structures cover on the shallow slot isolations in parallel at intervals. By utilizing the testing structure of the integrity of the semiconductor device gate oxide, the influences caused by the stress of adjacent parts at the edges of polysilicon gates and the shallow slot isolations on the gate oxide can be monitored, and the negative effects of the stress at the edges of the shallow slot isolations on the corrosion of the gate edges can be effectively avoided through defect analysis.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a test structure for the integrity of a gate oxide layer of a semiconductor device. Background technique [0002] With the continuous development of semiconductor technology, the thickness of the gate oxide layer of the MOS transistor in the integrated circuit is also reduced from 20-30nm to less than 1nm. The gate oxide layer continues to develop towards the film direction, but the power supply voltage should not be lowered, under a higher electric field strength. It is bound to make the performance of the gate oxide layer a prominent issue. Poor electrical resistance of gate oxide will lead to unstable electrical parameters of MOS devices, such as: drift of threshold voltage, decrease of transconductance, increase of leakage current, etc., which will further cause breakdown of gate oxide, leading to device failure and making the entire integrated circuit p...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66
Inventor 高超沈玺
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP