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Test structure for integrity of semiconductor element gate oxide

A technology of gate oxide layer and test structure, which is applied in the direction of semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc., can solve problems such as device failure, and achieve the effect of avoiding negative effects

Active Publication Date: 2013-09-25
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] The present invention aims to solve the problem that the gate oxide layer integrity test structure in the prior art ignores the defects near the edge of the gate oxide layer and the edge of the shallow trench isolation, which causes the device to fail due to defects in this part.

Method used

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  • Test structure for integrity of semiconductor element gate oxide
  • Test structure for integrity of semiconductor element gate oxide
  • Test structure for integrity of semiconductor element gate oxide

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Embodiment Construction

[0021] In order to make the technical features of the present invention more comprehensible, specific embodiments are given below in conjunction with the accompanying drawings to further describe the present invention.

[0022] An embodiment of the present invention provides a test structure for the integrity of the gate oxide layer of a semiconductor device. The test structure includes: an active region; In the region; the plurality of gate structures cover the shallow trench isolation in parallel and at intervals.

[0023] Wherein the gate structure includes: a gate and a gate oxide layer. The gate is polysilicon or metal gate. The gate oxide layer is an oxide layer, a nitride layer or a high dielectric constant material layer.

[0024] See Figure 3A , 3B, these two figures are schematic diagrams of the test structure for the integrity of the gate oxide layer of a semiconductor device with sparse isolation provided by an embodiment of the present invention. in Figure ...

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Abstract

The invention discloses a test structure for the integrity of a semiconductor element gate oxide, which comprises an active region, a plurality of blocky shallow slot isolators and a plurality of grid structures, wherein the blocky shallow slot isolators are arranged in the active region; and the grid structures cover the shallow slot isolators in parallel at intervals. By using the test structure for the integrity of the semiconductor element grid oxide, the influence on the gate oxide by the stress of the position near the edge of a polysilicon gate and the edges of the shallow slot isolators can be monitored, and the negative effect of the etching of the edges of the gate by the stress of the edges of the shallow slot isolators can be effectively avoided by defect analysis.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a test structure for the integrity of a gate oxide layer of a semiconductor device. Background technique [0002] With the continuous development of semiconductor technology, the thickness of the gate oxide layer of the MOS transistor in the integrated circuit is also reduced from 20-30nm to less than 1nm. The gate oxide layer continues to develop towards the film direction, but the power supply voltage should not be lowered, under a higher electric field strength. It is bound to make the performance of the gate oxide layer a prominent issue. Poor electrical resistance of gate oxide will lead to unstable electrical parameters of MOS devices, such as: drift of threshold voltage, decrease of transconductance, increase of leakage current, etc., which will further cause breakdown of gate oxide, leading to device failure and making the entire integrated circuit p...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/544
Inventor 高超
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP