Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Reliability test method

A test method and reliability technology, applied in static memory, instruments, etc., can solve the problems of time delay, long total time, and impact on chip production in mass production of chips

Inactive Publication Date: 2013-01-23
SEMICON MFG INT (SHANGHAI) CORP +1
View PDF1 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] It can be seen that the total time required for the above-mentioned endurance test is longer, and the cycle of the reliability test will also be longer
The longer reliability test cycle will delay the mass production of chips, thus affecting the chip production of foundries.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Reliability test method
  • Reliability test method
  • Reliability test method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach

[0017] refer to figure 2 Shown, a kind of embodiment of reliability testing method of the present invention comprises:

[0018] Step s1, selecting the number of samples for this reliability test and the number of test sectors in the test chip;

[0019] Step s2, according to the number of samples selected for this reliability test and the number of selected test sectors, the number of chips tested in this reliability test is obtained;

[0020] Step s3, performing this reliability test with the number of test chips and the number of test sectors,

[0021] Wherein, the number of samples of the reliability test is directly proportional to the product of the number of test chips in the reliability test and the number of test sectors in the test chip.

[0022] In the above reliability testing method, the number of samples of this reliability test is directly proportional to the product of the number of test chips in this reliability test and the number of test sectors in the test...

example 1

[0026] In this example, the existing reliability test mentioned above is used as a comparison. For the convenience of description, the number of non-volatile memory test chips selected in the existing reliability test method is N, and the number of test sectors in the corresponding test chip is n, while the non-volatile memory selected in the reliability test method of this example The number of memory test chips is M, and the number of test sectors in the corresponding test chip is m. According to the description of the reliability test method in the embodiment of the present invention, and assuming that in the reliability test of this example, the factors affecting the test results are exactly the same as those of the existing reliability test, for example, the test results are only affected by the performance of the memory cell array, then Have:

[0027] S=n×N=m×M (1)

[0028] In the conventional reliability test mentioned above, 64 non-volatile memory chips are selected ...

example 2

[0034] In Example 1, formula (1) is based on the assumption that the factors affecting the test results are exactly the same as the existing reliability tests. In some cases, the factors affecting the test results are not exactly the same with the number of test sectors. For example, for a non-volatile memory chip, it is not only the performance of the memory cell array that affects the test results, but also the performance of peripheral circuits. For example, in the process of cyclic writing and erasing operations on a non-volatile memory chip, both the memory cell array and peripheral circuits will be affected by stress. Therefore, the test sector is different, and the number of times of stress on the peripheral circuit is also different. Since the degradation of the performance of the peripheral circuit will also cause the failure of the test chip, the change of the number of test sectors will also lead to the change of the failure probability of the test chip.

[0035] ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a reliability test method, including: sample number used for the reliability test and the quantity of test sectors in a test chip are selected; the quantity of test chips in the reliability test is obtained according to the selected the sample number of the reliability test and the selected quantity of test sectors; and the reliability test is carried out according to thequantity of test chips and the quantity of test sectors; wherein the sample number of the reliability test is in proportion to product of the quantity of test chips in the reliability test and the quantity of test sectors in the test chip. The reliability test method reduces reliability test time, thus being beneficial to mass production of chip foundy.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a reliability testing method. Background technique [0002] At present, before mass production of chip products, reliability tests are required to verify the usability of the products. For example, reliability testing is performed on memory chips that need to be mass-produced to verify the usability of the memory chips. Chinese patent No. 01130670.X discloses a reliability testing method for non-volatile memory, which utilizes the physical characteristics of non-volatile memory with an insulating trap layer to perform accelerated testing and estimate service life. [0003] When performing a reliability test on, for example, a non-volatile memory chip, one of the tests is an endurance test. The endurance test generally includes the following steps: select a certain number of non-volatile memory chips as test samples, and in each test sample, select some test sectors to...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/00
Inventor 简维廷杨斯元张启华
Owner SEMICON MFG INT (SHANGHAI) CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products