Dual-loop tuning method for low-vibration high frequency difference frequency and phase locking and electrical architecture thereof

Abstract

The invention discloses a dual-loop tuning method for realizing low-vibration high frequency difference frequency and phase locking and an electrical architecture thereof. The electrical architecture comprises dual loops used for respectively tuning frequency and phase. The method comprises the steps of: determining a total real-time phase error between a reference clock and a feedback clock by an interpolator and a phase and frequency detector; separating and extracting the total real-time phase error into a real-time phase error with two frequency components, namely static / low frequency offset and modulation frequency offset, by a low-pass filter; tracking the static / low frequency offset through a frequency locking loop by the real-time phase error of the static / low frequency offset; and tracking whether the phase between the reference clock and the feedback clock is aligned or not through a phase locking loop by using the real-time phase error of the modulation frequency offset and the clock phase outputted by the frequency locking loop. The dual-loop frequency and phase locking architecture can effectively avoid the increase of high-frequency vibration without increasing loop gain or bandwidth.

Description

technical field [0001] The present invention relates to a clock and data recovery technology in the field of data communication, in particular to a double-loop frequency-locking and phase-locking method and its electrical structure for maintaining phase locking and slowing down large-scale jitter under fixed or serious modulation frequency misalignment in data communication. belongs to the field of electricity. Background technique [0002] In the design of modern high-speed data communication systems, clock recovery is widely used by embedding clock timing information in the original data stream. It offers higher data rates, better reliability, reduced noise generation, improved noise immunity and lower power costs. To further reduce electromagnetic interference (EMI), spread spectrum clocking (SSC) technology is used to distribute the energy into a limited frequency band. The clock frequency is adjusted to a lower frequency, such as 30kHz to 33kHz in the PCI-Express prot...

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Problems solved by technology

But the higher clock recovery bandwidth leads to excessive loop gain, which increases the high frequency jitter of the recovered clock

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