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Adapting word line pulse widths in memory systems

A memory system, pulse width technology, applied in the field of memory systems, which can solve problems such as performance loss and additional power consumption impact, large test time, etc.

Inactive Publication Date: 2010-12-22
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, a large loss of performance and additional power consumption can affect most ICs produced
Another limitation is the large test time required to measure the large sample size required to accurately determine the value of the optimal WL pulse width for a given target yield

Method used

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  • Adapting word line pulse widths in memory systems
  • Adapting word line pulse widths in memory systems
  • Adapting word line pulse widths in memory systems

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Embodiment Construction

[0020] Aspects of embodiments of the invention are disclosed in the following description and associated drawings directed to specific embodiments of the invention. Alternative embodiments may be devised without departing from the scope of the invention. Additionally, well-known elements of the invention will not be described in detail or will be omitted so as not to obscure the relevant details of the invention.

[0021] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term "embodiments of the invention" does not require that all embodiments of the invention include the discussed feature, advantage or mode of operation.

[0022] As discussed in the Background, conventional approaches to optimize word line (WL) pulse widths for memory systems in a given batch of integrated circuits ...

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Abstract

Systems, circuits and methods for adapting word line (WL) pulse widths used in memory systems are disclosed. One embodiment of the invention is directed to an apparatus comprising a memory system. The memory system comprises: a memory operating according to a wordline (WL) pulse with an associated WL pulse width; a built-in self-test (BIST) unit that interfaces with the memory, the BIST unit being configured to run a self-test of the internal functionality of the memory and provide a signal indicating if the memory passed or failed the self-test; and an adaptive WL control circuit that interfaces with the BIST unit and the memory, the adaptive WL control circuit being configured to adjust the WL pulse width of the memory based on the signal provided by the BIST unit.

Description

[0001] Claim of priority under 35 U.S.C. §119 [0002] This patent application claims the 61st / Priority to Provisional Application No. 014,257, assigned to the present assignee and expressly incorporated herein by reference. technical field [0003] Embodiments of the invention relate to memory systems. More particularly, embodiments of the invention relate to adapting word line pulse widths used in memory systems. Background technique [0004] As CMOS technology continues to scale to smaller dimensions, process variation due to process control limitations as well as fundamental physical limitations tends to increase. Embedded memories, such as embedded SRAM, are especially susceptible to large process variations due to aggressive design rules and their small size compared to other digital logic. To cope with this large increase in process variation, memory circuit designers typically use overly conservative design approaches in order to achieve high parametric and func...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/50
CPCG11C8/08G11C29/50012G11C29/028G11C7/22G11C2029/1202G11C29/50G11C2029/0407G11C7/12G11C29/12
Inventor 穆罕默德·H·阿布-拉赫马杨赛森
Owner QUALCOMM INC
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