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Mechanism for broadcasting system management interrupts to other processors in a computer system

A technology of broadcasting system and system management mode, which is applied in the field of interrupt processing of system management

Active Publication Date: 2011-01-05
ADVANCED MICRO DEVICES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This situation can cause problems in a multiprocessor environment

Method used

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  • Mechanism for broadcasting system management interrupts to other processors in a computer system
  • Mechanism for broadcasting system management interrupts to other processors in a computer system
  • Mechanism for broadcasting system management interrupts to other processors in a computer system

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Embodiment Construction

[0010] see figure 1 , is a block diagram showing one embodiment of the electronic computing system 10. In the illustrated embodiment, the electronic computing system 10 includes a processing node 12 coupled to memory 14 and input / output (I / O) hubs 13A and 13B. The node 12 includes processor cores 15A and 15B coupled to a node controller 20, which is also coupled to a memory controller 22; a plurality of HyperTransport TM (HT) interface circuits 24A to 24C; and a third layer (L3) shared cache 60 . The HT circuit 24C is coupled to the I / O hub 16A, which is coupled to the I / O hub 16A in a daisy-chain configuration (using the HT interface in this embodiment). I / O hub 16B. The remaining HT interface circuits 24A and 24B can be connected via other HT interfaces (in figure 1 not shown) is connected to other similar processing nodes (in figure 1 not shown in ). The memory controller 22 is coupled to the memory 14 . In one embodiment, node 12 may include the figure 1 A single i...

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Abstract

A computer system (10) includes a system memory (14), a plurality of processor cores (15A, 15B), and an input / output (I / O) hub (13A) that may communicate with each of the processor cores. In response to detecting an occurrence of an internal system management interrupt (SMI), each of the processor cores may save to a system management mode (SMM) save state in the system memory, information corresponding to a source of the internal SMI. In response to detecting the internal SMI, each processor core may further initiate an I / O cycle to a predetermined port address within the I / O hub. The I / O hub may broadcast an SMI message to each of the processor cores in response to receiving the I / O cycle. Each of the processor cores may further save to the SMM save state in the system memory, respective internal SMI source information in response to receiving the broadcast SMI message.

Description

technical field [0001] The present invention relates to multi-processor electronic computing systems, and in particular, to interrupt handling for system management. Background technique [0002] Many processors include a system management mode (SMM) that allows the processor to operate in alternate environments, such as for monitoring, managing system resources, power usage, and running certain system-level code ( system level code). Typically, the SMM can enter a system management interrupt (SMI for short). The SMM may include an SMI handler to handle the interrupt. Many common processors include physical SMI package pins to drive the processor into SMM mode when an appropriate voltage is applied to the pins. Additionally, there are internal SMI sources such as processor thermal notifications that can cause the processor to enter SMM. [0003] Generally speaking, when the processor enters SMM, the current processor state will be stored in a specific area of ​​the memor...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/24
CPCG06F13/24
Inventor M·T·克拉克J·伊利克
Owner ADVANCED MICRO DEVICES INC