Method for implementing digital GSM time slot ALC
An implementation method and digital technology, applied in power management, wireless communication, electrical components, etc., can solve the problems of large power difference and inability to correctly reflect the maximum single time slot power
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[0016] Below in conjunction with accompanying drawing and embodiment the present invention will be further described:
[0017] figure 1 It is a schematic diagram of the system principle of the present invention; the system is a part of a digital repeater, including a radio frequency signal attenuator, an analog mixer, an analog / digital converter and an FPGA (Field-Programmable GateArray-field-programmable gate array). The signal passes through these devices in turn, and the ALC algorithm is completed inside the FPGA, and then the control signal is sent to the attenuator.
[0018] The FPGA internal ALC algorithm is mainly divided into two modules - the single slot power statistics module ( figure 2 ), attenuation logic control module ( image 3 ).
[0019] Single slot power statistics module, see figure 2 , the signal mainly passes through: squaring, single-slot power statistics, power comparison, and maximum output power. The specific process is as follows:
[0020] 1....
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