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Chip test board and test method, and DFN packaging device test board and test method

A chip testing and testing board technology, which is applied to the components of electrical measuring instruments, measuring devices, electronic circuit testing, etc. small effect

Inactive Publication Date: 2011-02-16
上海天臣威讯信息技术有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the disadvantages of the fixture are obvious: large volume, troublesome production, inconvenient maintenance, and relatively high cost
Moreover, many mechanical parts are used in the production of the jig, and it is easy to be damaged after long-term operation.

Method used

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  • Chip test board and test method, and DFN packaging device test board and test method
  • Chip test board and test method, and DFN packaging device test board and test method
  • Chip test board and test method, and DFN packaging device test board and test method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0027] see figure 1 , the present invention discloses a DFN packaging device test board, the test board includes a test board main body, at least two rows of pogo pins 11, 12 arranged on the test board main body; the pogo pins need to be tested according to the DFN device 20 The number of pins and pin spacing are arranged, and soldered to the corresponding position on the test board.

[0028] When testing and installing, the pads on one side of the DFN device 20 are first aligned with the corresponding row of pogo pins 11 and pushed down, then the DFN device 20 is put down on the test board as a whole, and the other row of pogo pins 12 withstands the pads on the other side .

[0029] The DFN packaged device test board of the present invention has been introduced above, and the present invention discloses a test method utilizing the above-mentioned DFN packaged device test board at the same time; please refer to figure 2 , the test method comprises the steps of:

[0030] A....

Embodiment 2

[0035] The present invention uses the double-row pogo pins on the test board to replace the test fixture, and the pogo pins must be selected with good electrical conductivity. The test board made of spring thimble, the test method is as follows:

[0036] Thin spring ejector pins are used on the test board, and the spring ejector pins are arranged according to the number of pins and the pitch of the pins of the DFN packaged products and soldered to the corresponding positions on the test board. When testing and installing, the pads on one side of the DFN package product are first aligned with the corresponding row of thimbles and pushed down, and then the product is put down against the test board as a whole, and the other row of thimbles will easily withstand the pads on the other side. This method makes it very convenient to replace products when many products are tested with the same test board, and the operation is very simple. Moreover, the advantages of making a matching...

Embodiment 3

[0040] This embodiment discloses a chip test board, the test board includes a test board main body, at least two rows of test thimbles arranged on the test board main body; The dimensions are arranged and connected to the corresponding positions on the test board.

[0041] In this embodiment, the test thimble is a pogo pin. Two rows of test thimbles are arranged on the main body of the test board.

[0042] When testing and installing, the pads on one side of the chip are first aligned with the corresponding row of test thimbles and pushed down, then the chip is put down on the test board as a whole, and the other row of test thimbles withstands the pads on the other side.

[0043] This embodiment discloses a chip testing method at the same time, and the testing method includes the following steps:

[0044] 1. Set at least two rows of test thimbles on the main body of the chip test board; the test thimbles are arranged according to the number of pins to be tested on the chip ...

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Abstract

The invention discloses a DFN packaging device test board and a test method. The test board comprises a test board main body and at least two rows of spring center ejector pins arranged on the test board main body, wherein the spring ejector pins are arranged according to the quantity of base pins to be tested on the DFN device and the space between base pins, and welded in the corresponding positions on the test board. In the test installation process, the pad on one side of the DFN device is firstly aligned with one row of spring ejector pins and pushed down; the integral DFN device is put down against the test board; and the other row of spring ejector pins are abutted against the pad on the other side. When at least two rows of test ejector pins are arranged on the test board main body, the DFN packaging device test board can be used for conveniently testing DFN devices and other packaging chips. The invention has the advantages of small size, simple manufacture, low cost, and simple and convenient use.

Description

technical field [0001] The invention belongs to the technical field of packaging and testing, and relates to a chip testing board, in particular to a DFN packaging device testing board; meanwhile, the present invention relates to a testing method for a chip testing board, and in addition, the present invention also relates to a testing method for a DFN packaging device testing board . Background technique [0002] DFN / QFN is a newest electronic packaging process. Various components of ON Semiconductor have adopted advanced bilateral or square flat lead-free packaging (DFN / QFN). The DFN / QFN platform is the latest surface mount packaging technology. The mounting pad, solder mask, and stencil pattern design of the printed circuit board (PCB), as well as the assembly process, all need to follow the corresponding principles. [0003] The DFN / QFN platform has the versatility to allow one or more semiconductor devices to be connected in a lead-free package. [0004] At present, ...

Claims

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Application Information

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IPC IPC(8): G01R1/073G01R31/28
Inventor 徐承军贠志强吝忠锋
Owner 上海天臣威讯信息技术有限公司
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