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Manufacturing method of semiconductor device and semiconductor device

A manufacturing method and semiconductor technology, applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., and can solve problems such as non-disclosure

Active Publication Date: 2012-10-10
키오시아가부시키가이샤
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, there is no disclosure of a specific process for selectively forming this structure only on the second terminal.

Method used

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  • Manufacturing method of semiconductor device and semiconductor device
  • Manufacturing method of semiconductor device and semiconductor device
  • Manufacturing method of semiconductor device and semiconductor device

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Experimental program
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Embodiment Construction

[0037] According to the present invention, a photosensitive resin film is modified on a substrate having electrode terminals as a first conductive layer to form an insulating layer having first openings and second openings reaching the electrode terminals. Next, a second conductive layer electrically connected to the electrode terminal is formed on the insulating layer including the first opening, and a third conductive layer is formed on the second conductive layer. The oxidation-reduction potential of the third conductive layer and the first conductive layer The difference is smaller than the difference between the oxidation-reduction potentials of the first conductive layer and the second conductive layer. Next, modify the photosensitive resin film to form an insulating layer having a third opening reaching the third conductive layer and a fourth opening reaching the electrode terminal through the second opening, and forming bumps electrically connected to the third conducti...

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PUM

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Abstract

According to one embodiment, a manufacturing method of a semiconductor device attained as follows. A dielectric layer having a first opening and a second opening reaching an electrode terminal is formed by modifying a photosensitive resin film on a substrate on which the electrode terminal of a first conductive layer is provided. Next, a second conductive layer that is electrically connected to the electrode terminal is formed on the dielectric layer that includes inside of the first opening, and a third conductive layer that has an oxidation-reduction potential of which difference from the oxidation-reduction potential of the first conductive layer is smaller than a difference of the oxidation-reduction potential between the first conductive layer and the second conductive layer is formed on the second conductive layer. Next, a dielectric layer having a third opening reaching the third conductive layer and a fourth opening reaching the electrode terminal via the second opening is formed by modifying a photosensitive resin film, and a bump that is electrically connected to the third conductive layer is formed.

Description

[0001] This application has the benefit of priority of Japanese Patent Application No. 2009-178179 filed on July 30, 2009 and Japanese Patent Application No. 2010-143085 filed on June 23, 2010, the entirety of which is The contents are all cited in this application. technical field [0002] The present invention generally relates to a method of manufacturing a semiconductor device and a semiconductor device. Background technique [0003] In recent years, in order to achieve high integration and high functionality of semiconductor devices, it is required to increase the operating speed of the devices and increase the capacity of the memory. Recently, instead of eDRAM (Embedded Dynamic Random Access Memory: Embedded Dynamic Random Access Memory) of the chip, a COC (Chip on Chip) device in which a logic chip and a large-capacity DRAM are stacked has also been developed. [0004] In a COC device, two types of terminals, terminals for connecting to another chip (hereinafter refe...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/485H01L21/60
CPCH01L2224/16145H01L2224/73207H01L2924/01025H01L2224/48666H01L2224/13147H01L2224/13099H01L2924/01022H01L2224/0401H01L2224/1147H01L2924/01028H01L2224/13083H01L2924/01013H01L2924/0103H01L2224/2919H01L24/06H01L24/81H01L2224/73204H01L24/48H01L2224/05548H01L2224/13155H01L24/32H01L2924/01033H01L2224/32145H01L2924/01074H01L2924/01078H01L2924/01073H01L2224/11462H01L2924/01023H01L2224/0603H01L2924/01082H01L24/73H01L2224/05569H01L2224/73215H01L2224/05666H01L2924/01327H01L2924/01019H01L2924/01029H01L2924/00013H01L2224/02311H01L2224/11849H01L2224/05008H01L2924/01027H01L24/11H01L2924/014H01L2224/81191H01L2224/05571H01L2924/01024H01L2224/05572H01L2224/06051H01L2924/01079H01L24/05H01L24/03H01L2224/04042H01L2924/14H01L2924/01005H01L2924/01006H01L2924/01011H01L2924/01014H01L24/16H01L2224/45144H01L2224/02381H01L2224/13111H01L2924/0002H01L2924/00014H01L24/45H01L2224/13599H01L2224/05599H01L2224/05099H01L2224/29099H01L2224/29599H01L2924/00H01L2224/05552H01L2224/45015H01L2924/207
Inventor 山下创一右田达夫饭岛匡宫田雅弘内田雅之栂嵜隆江泽弘和
Owner 키오시아가부시키가이샤