High-speed comparer LATCH circuit

Abstract

The invention relates to a high-speed comparer LATCH circuit which comprises a current source, a first MOS (Metal Oxide Semiconductor) transistor , a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor and a sixth MOS transistor, wherein the source electrode of the first MOS transistor and the source electrode of the second MOS transistor are connected with the current source, grid electrodes of the first and the second MOS transistors are respectively used for receiving a first input voltage and a second input voltage, drain electrodes of the first and the second MOS transistors are respectively connected with source electrodes of the third and the fourth MOS transistors, the drain electrode of the third MOS transistor and the grid electrode of the fourth MOS transistor as well as the grid electrode of the sixth MOS transistor are respectively connected with the drain electrode of the fifth MOS transistor, the drain electrode of the fourth MOS transistor and the grid electrode of the third MOS transistor as well as the grid electrode of the fifth MOS transistor are respectively connected with the drain electrode of the sixth MOS transistor, and the source electrode of the fifth MOS transistor and the source electrode of the sixth MOS transistor are grounded. The invention can improve the conversion speed of the last stage of LATCH of a high-speed comparer, and acutely reduce the kick noise when the LATCH turns.

Description

technical field [0001] The invention relates to microelectronic circuits, in particular to a high-speed comparator LATCH (latch) circuit. Background technique [0002] like figure 1 As shown, the LATCH circuit commonly used in the industry mainly forms a LATCH through two pairs of MOS transistors M3, M4, M5, and M6 under positive feedback. Among them, the PMOS transistors M1 and M2 are the input transistors of the LATCH, and the voltages Vin1 and Vin2 are two input transistors. Level, point X and point Y are the inflow points where the input current flows to the LATCH core, making the MOS transistors M3, M4, M5, and M6 form positive feedback. Just because the output points are at points X and Y, the voltage variation range and frequency of points X and Y are quite large. The disadvantage of this comparator structure is that the reverse kickback noise will be large and the conversion speed is not the fastest. [0003] A common solution in the industry is to place a pair of ...

AI Technical Summary

Problems solved by technology

Just because the output points are at points X and Y, the voltage variation range and frequency of points X and Y are quite large. The disadvantage of this comparator structure is that the reverse kickback noise will be large and the conversion speed is not the fastest.

[0003] A common solution in the industry is to place a pair of PMOS transistors under the pair of input PMOS transistors to form a CASCODE (cascode) structure; although this structure can slightly reduce the kickback noise, the point X or Y is converted to In the high-level stage, the corresponding input tube M1 or M2 will enter the linear region, and the reduction of the conversion speed has not been improved; especially when the two input levels Vin1 and Vin2 are very low, the speed is particularly affected. obvious

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