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Semiconductor packaging technology

A packaging process and semiconductor technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve problems such as vulnerability to etching attacks

Active Publication Date: 2013-08-21
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the exposed adhesive material near the edge of the die is vulnerable to etch attack, causing problems during temporary carrier bonding and de-bonding
An edge seal layer is traditionally provided at the edge of the bond material, but the subsequent wafer thinning process will expose another portion of the bond material adjacent to the edge of the wafer

Method used

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  • Semiconductor packaging technology
  • Semiconductor packaging technology
  • Semiconductor packaging technology

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Embodiment Construction

[0025] The description of "an embodiment" in this specification means that the specific object, structure or characteristic described in this embodiment is included in at least one embodiment. Therefore, "in an embodiment" in multiple places in this specification does not necessarily refer to the same embodiment. In addition, there may be a particular combination of items, structures or characteristics, under appropriate conditions, in one or more embodiments. It should be noted that the following drawings are not drawn to scale and are for illustrative purposes only.

[0026] here Figure 1A to Figure 1F is a series of cross-sectional views illustrating an embodiment of a die-to-wafer stack formed with a protective layer of adhesive material at the edge of the wafer.

[0027] Figure 1A It is a cross-sectional view of an embodiment of attaching the chip 10 on the carrier 12 by the adhesive layer 14 . A wafer 10 is provided having a plurality of semiconductor chips thereon...

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PUM

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Abstract

This description relates to a semiconductor device including a wafer having a first surface and a second surface opposite to the first surface and a carrier attached to the first surface of the wafer by an adhesive layer, a portion of the adhesive layer adjacent to an edge of the wafer is exposed. The semiconductor device further includes a protection layer to cover the exposed portion of the adhesive layer. The semiconductor device further includes a plurality of dies attached to the second surface and a molding compound encapsulating the plurality of dies.

Description

technical field [0001] The present invention relates to the fabrication of semiconductor devices, and more particularly to the fabrication of three-dimensional (3D) integrated circuits (ICs). Background technique [0002] The semiconductor industry has experienced continued rapid growth due to continued improvements in the mobility of various electronic components (ie, transistors, diodes, resistors, capacitors, etc.). For the most part, aggressiveness improvements have come from ever-shrinking minimum line widths, allowing more components to fit into a given area. The three-dimensional integrated circuit can solve the limitation of the number and length of interconnections between devices when the number of devices increases. One method of forming three-dimensional integrated circuits is die-to-wafer stack bonding, where one or more die is bonded to the wafer, and the size of the die can be smaller than the size of the chips on the wafer. Efforts are currently being made ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/50H01L21/56
CPCH01L21/6836H01L25/50H01L2924/0105H01L2224/81001H01L24/81H01L21/76898H01L2221/68381H01L24/94H01L2224/81801H01L23/49811H01L2924/09701H01L2924/01327H01L2924/01033H01L2225/06513H01L2924/01006H01L2225/06541H01L2924/01029H01L2924/10329H01L2221/6834H01L2924/19041H01L2924/014H01L21/561H01L2924/181H01L2924/14H01L2924/00
Inventor 邱文智吴文进眭晓林
Owner TAIWAN SEMICON MFG CO LTD