Synchronous oscillator, clock recovery apparatus, clock distribution circuit, and multi-mode injection circuit

Abstract

Disclosed herein is a synchronous oscillator including at least one injection circuit having an injection signal input terminal, an internal clock signal input terminal, and a clock output terminal, and at least one delay circuit cascaded to the injection circuit.

Description

Technical field [0001] The present invention relates to a synchronous oscillator, a clock recovery device, a clock distribution circuit and a multi-mode injection circuit for outputting a clock signal. Background technique [0002] Recently, in the field of digital transmission, the demand for high-speed and low-power transmission of large amounts of data has been increasing. For interfaces used for such data transmission, clock recovery devices are widely used. [0003] At the same time, due to the increased jitter component contained in the signal caused by the increased transmission rate, the ability to resist the jitter of the high-speed interface is desired. [0004] Clock recovery includes those based on PLL applications, as well as selecting or generating a clock with phase locked to the received data signal from a multi-phase clock signal. [0005] However, these clock recovery schemes involve the problem that high-speed operation requires a phase comparator that operates at ...

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Problems solved by technology

[0005] However, these clock recovery schemes involve a problem that high-speed operation requires a phase comparator that operates at high speed, making it difficult to achieve high-speed operation of the clock recovery device

[0006] In addition, because these schemes are implemented based on negative feedback for locking with the received data signal, it takes a considerable time to synchronize the clock signal with the received data signal, making these schemes unsuitable for applications that need to be synchronized with the received data signal in a relatively short period of time. Transmission of burst data with data signal locked

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